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SN74LVCE161284DGGR

SN74LVCE161284DGGR

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Texas Instruments

19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

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SN74LVCE161284DGGR

SN74LVCE161284DGGR

Active
Texas Instruments

19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

Find alt

Description

General part information

74LVCE161284 Series

The SN74LVCE161284 is designed for 3-V to 3.6-V VCCoperation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCE161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-kintegrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCCCABLE. If VCCCABLE is off, PERI LOGIC OUT is set to low.

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVCE161284DGGR
Logic TypeIEEE STD 1284 Translation Transceiver
Mounting TypeSurface Mount
Number of Bits19 bits
Operating Temperature (Max)70 °C
Operating Temperature (Min)0 °C
Package Length0.24 in
Package Name48-TSSOP, 48-TFSOP
Package Width6.1 mm
Supply Voltage (Max)3.6 V
Supply Voltage (Min)3 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

CMOS Power Consumption and CPD Calculation (Rev. B)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Live Insertion
STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS
Implications of Slow or Floating CMOS Inputs (Rev. E)
Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators
Selecting the Right Level Translation Solution (Rev. A)
Signal Switch Data Book (Rev. A)
Standard Linear & Logic for PCs, Servers & Motherboards
Understanding Advanced Bus-Interface Products Design Guide
Input and Output Characteristics of Digital Integrated Circuits
Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators
Design Summary for WCSP Little Logic (Rev. B)
Little Logic Guide 2018 (Rev. G)
LVC Characterization Information
LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)
Texas Instruments Little Logic Application Report
16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
How to Select Little Logic (Rev. A)
Use of the CMOS Unbuffered Inverter in Oscillator Circuits
Voltage Translation Buying Guide (Rev. A)
Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A)
SN74LVCE161284 datasheet
LOGIC Pocket Data Book (Rev. B)
Low-Voltage Logic (LVC) Designer's Guide
TI IBIS File Creation, Validation, and Distribution Processes
Logic Guide (Rev. AB)
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
SN74LVCE161284DGGR | Datasheet