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OMFCBGA (GNY)

TMS320C6203BGNY30C

Obsolete
Texas Instruments

C62X FIXED POINT DSP- UP TO 300MHZ, 896KB

Find alt
OMFCBGA (GNY)

TMS320C6203BGNY30C

Obsolete
Texas Instruments

C62X FIXED POINT DSP- UP TO 300MHZ, 896KB

Find alt

Description

General part information

TMS320 Series

The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B, TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.(1)

Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic.

Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices.

Technical Specifications

Parameters and characteristics for this part

SpecificationTMS320C6203BGNY30C
Clock Rate (Frequency)300 MHz
InterfaceMcBSP
Mounting TypeSurface Mount
Non-Volatile Memory TypeExternal
On-Chip RAM896 kB
Operating Temperature (Max)90 °C
Operating Temperature (Min)0 °C
Package / Case384-FBGA, FCCSPBGA
Package Length18 mm
Package Name384-FC/CSP
Package Width18 mm
TypeFixed Point
Voltage - Core1.5 V
Voltage - I/O3.3 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

G.729/A Speech Coder: Multichannel TMS320C62x Implementation (Rev. B)
TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)
Migrating across the TMS320C6202/02B/03B/04 DSPs (Rev. D)
TMS320C6000 Expansion Bus Host Interface Performance
TMS320C62x DSP Expansion Bus (XBUS) Reference Guide (Rev. A)
MPEG-2 Video Decoder: TMS320C62x (TM) DSP Implementation
TMS320C6000 McBSP as a TDM Highway (Rev. A)
TMS320C6000 Board Design: Considerations for Debug (Rev. C)
TMS320C6000 Expansion Bus: Multiple DSPs to i80960Kx/Jx Microproessor Interface (Rev. A)
TMS320C6000 McBSP Initialization (Rev. C)
ETSI Math Operations in C for the TMS320C62x (Rev. A)
TMS320C6000 Memory Test (Rev. A)
TMS320C6000 DSP Interrupt Selector Reference Guide (Rev. A)
TMS320C6000 Board Design for JTAG (Rev. C)
TMS320C62x DSP CPU and Instruction Set Reference Guide (Rev. A)
TMS320C6000 EMIF to External Flash Memory (Rev. A)
TMS320C6000 Expansion Bus Interface to PCI Bus Through PLX PCI9080 (Rev. A)
TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C)
TMS320C6000 u-Law and a-Law Companding with Software or the McBSP
G.723.1 Dual Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B)
TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)
TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)
Introduction to TMS320C6000 DSP Optimization
TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B)
TMS320C6000 C Compiler: C Implementation of Intrinsics
GSM Enhanced Full Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B)
General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point
TMS320C620x/C670x DSP Boot Modes and Configuration Reference Guide
TMS320C6000 McBSP: I2S Interface
TMS320C6000 CPU and Instruction Set Reference Guide (Rev. G)
TMS320C6000 Expansion Bus to Intel80960Kx/Jx Microprocessor Interface (Rev. B)
How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)
TMS320C6000 Expansion Bus to MC68360 Microprocessor Interface (Rev. A)
TMS320C6203B Fixed-Point Digital Signal Processor datasheet (Rev. N)
TMS320C6000 Expansion Bus: Multiple DSP Connection Using Asynchronous (Rev. A)
TMS320C6000 McBSP: IOM-2 Interface (Rev. A)
On the Implementation of MPEG-4 Motion Compensation Using the TMS320C62x
TMS320C620x/C670x DSP Program & Data Memory Controller/DMA Controller Ref.Guide (Rev. A)
IS-127 Enhanced Var Rate Speech Coder:Multichannel TMS320C62x Implementation (Rev. B)
TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)
TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E)
TMS320C6000 DSP Designing for JTAG Emulation Reference Guide
Thermal Considerations for the DM64xx, DM64x, and C6000 Devices
Circular Buffering on TMS320C6000 (Rev. A)
TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q)
TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)
TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)
Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)
TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G)
TMS320C6000 Expansion Bus to MPC860 Microprocessor Interface (Rev. B)
TMS320C620x/C642x McBSP: UART (Rev. C)
TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)
TMS320C6203, TMS320C6203B DSPs Silicon Errata (Silicon Rev. 1.x, 2.x, 3.0, 3.1) (Rev. L)
Extended Precision Radix-4 Fast Fourier Transform Implemented on the TMS320C62x
TMS320C6000 System Clock Circuit Example (Rev. A)
Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A)
Using a TMS320C6000 McBSP for Data Packing (Rev. A)
TMS320C620x/TMS3206701 DMA and CPU: Data Access Performance (Rev. A)
Using IBIS Models for Timing Analysis (Rev. A)
TMS320C6000 DMA Example Applications (Rev. A)