ZL30120GGG
ActiveIC LINE CARD SYNCH 100CABGA
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ZL30120GGG
ActiveIC LINE CARD SYNCH 100CABGA
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | ZL30120GGG | ZL30120 Series |
|---|---|---|
| Differential - Input:Output | False | False |
| Input | LVCMOS | LVCMOS |
| Main Purpose | SONET/SDH, Telecom, Ethernet | SONET/SDH, Telecom, Ethernet |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 85 °C | 85 °C |
| Operating Temperature [Min] | -40 °C | -40 °C |
| Output | LVCMOS | LVCMOS |
| Package / Case | 100-FBGA | 100-FBGA |
| PLL | True | True |
| Ratio - Input:Output | 11:10 | 11:10 |
| Supplier Device Package | 100-CABGA (9x9) | 100-CABGA (9x9) |
| Voltage - Supply [Max] | 3.63 V | 3.63 V |
| Voltage - Supply [Min] | 2.97 V | 2.97 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
ZL30120 Series
SONET/SDH Line Card System Synchronizer
| Part | Operating Temperature [Max] | Operating Temperature [Min] | Output | Input | Number of Circuits | Ratio - Input:Output | Differential - Input:Output | Mounting Type | Package / Case | PLL | Supplier Device Package | Main Purpose | Voltage - Supply [Min] | Voltage - Supply [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Microchip Technology ZL30120GGG2 | 85 °C | -40 °C | LVCMOS | LVCMOS | 1 | 11:10 | Surface Mount | 100-FBGA | 100-CABGA (9x9) | Ethernet, SONET/SDH, Telecom | 2.97 V | 3.63 V | ||
Microchip Technology ZL30120GGG | 85 °C | -40 °C | LVCMOS | LVCMOS | 1 | 11:10 | Surface Mount | 100-FBGA | 100-CABGA (9x9) | Ethernet, SONET/SDH, Telecom | 2.97 V | 3.63 V |
Description
General part information
ZL30120 Series
The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.
**[Click here for secure documentation](https://www.microsemi.com/product-directory/cgcd-mature/4715-zl30120#resources)**
Documents
Technical documentation and resources
No documents available