SN74LVC10APW
ActiveTexas Instruments
THREE-CHANNEL, THREE-INPUT, 1.65V TO 3.6V NAND GATES
SN74LVC10APW
ActiveTexas Instruments
THREE-CHANNEL, THREE-INPUT, 1.65V TO 3.6V NAND GATES
Description
General part information
74LVC10 Series
This triple 3-input positive-NAND gate is designed for 1.65V to 3.6V VCC operation.
This triple 3-input positive-NAND gate is designed for 1.65V to 3.6V VCC operation.
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LVC10APW |
|---|---|
| Current - Output High | 24 mA |
| Current - Output Low | 24 mA |
| Current - Quiescent (Max) | 1 µA |
| Input Logic Level - High (Max) | 2 V |
| Input Logic Level - High (Min) | 1.7 V |
| Input Logic Level - Low (Max) | 0.8 V |
| Input Logic Level - Low (Min) | 0.7 V |
| Logic Type | NAND Gate |
| Max CL | 50 pF |
| Max Propagation Delay | 4.7 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 3 |
| Number of Inputs | 3 |
| Operating Temperature (Max) | 125 °C |
| Operating Temperature (Min) | -40 °C |
| Package Length | 0.173 in |
| Package Name | 14-TSSOP |
| Package Width | 4.4 mm |
| Voltage - Supply (Maximum) | 3.6 V |
| Voltage - Supply (Minimum) | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Sign in to see pricing
Create a free account to access distributor pricing data.
CAD
3D models and CAD resources for this part
Documents
Technical documentation and resources
SN74LVC10A Triple 3-Input Positive-NAND Gate datasheet (Rev. Q)
LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)
Standard Linear & Logic for PCs, Servers & Motherboards
Signal Switch Data Book (Rev. A)
Input and Output Characteristics of Digital Integrated Circuits
Texas Instruments Little Logic Application Report
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
Selecting the Right Level Translation Solution (Rev. A)
STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS
LOGIC Pocket Data Book (Rev. B)
Live Insertion
16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
How to Select Little Logic (Rev. A)
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
Design Summary for WCSP Little Logic (Rev. B)
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
LVC Characterization Information
Understanding Advanced Bus-Interface Products Design Guide
TI IBIS File Creation, Validation, and Distribution Processes
Little Logic Guide 2018 (Rev. G)
CMOS Power Consumption and CPD Calculation (Rev. B)
Use of the CMOS Unbuffered Inverter in Oscillator Circuits
Implications of Slow or Floating CMOS Inputs (Rev. E)
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Low-Voltage Logic (LVC) Designer's Guide
Logic Guide (Rev. AB)
