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CD54HCT193F3A - SNJ54HC193J

CD54HCT193F3A

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Texas Instruments

HIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS 4-BIT BINARY UP/DOWN COUNTERS

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CD54HCT193F3A - SNJ54HC193J

CD54HCT193F3A

Active
Texas Instruments

HIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS 4-BIT BINARY UP/DOWN COUNTERS

Technical Specifications

Parameters and characteristics for this part

SpecificationCD54HCT193F3A
Count Rate29 MHz
DirectionDown, Up
Logic TypeBinary Counter
Mounting TypeThrough Hole
Number of Bits per Element4
Number of Elements [custom]1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 C
Package / Case16-CDIP (0.300", 7.62mm)
ResetAsynchronous
Supplier Device Package16-CDIP
TimingSynchronous
Trigger TypePositive Edge
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

CD54HCT193 Series

High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counters

PartOperating Temperature [Min]Operating Temperature [Max]TimingDirectionVoltage - Supply [Max]Voltage - Supply [Min]Count RateNumber of Bits per ElementTrigger TypePackage / CaseLogic TypeNumber of Elements [custom]ResetMounting TypeSupplier Device Package
Texas Instruments
CD54HCT193F3A
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively. Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter. If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively. Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter. If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
-55 C
125 °C
Synchronous
Down, Up
5.5 V
4.5 V
29 MHz
4
Positive Edge
16-CDIP (0.300", 7.62mm)
Binary Counter
1
Asynchronous
Through Hole
16-CDIP

Description

General part information

CD54HCT193 Series

The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.

Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.

If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.