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SSOP (DL)

SN74LVC16373ADLR

Active
Texas Instruments

16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SSOP (DL)

SN74LVC16373ADLR

Active
Texas Instruments

16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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Description

General part information

74LVC16373 Series

This 16-bit transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation.

The SN74LVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVC16373ADLR
Circuit8:8
Current - Output High24 mA
Current - Output Low24 mA
Delay Time - Propagation2.1 ns
Independent Circuits2
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature (Max)85 °C
Operating Temperature (Min)-40 °C
Output TypeTri-State
Package Length0.295 in
Package Name48-SSOP, 48-BSSOP
Package Width7.5 mm
Voltage - Supply (Maximum)3.6 V
Voltage - Supply (Minimum)1.65 V

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

Live Insertion
LVC Characterization Information
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
Logic Guide (Rev. AB)
Implications of Slow or Floating CMOS Inputs (Rev. E)
Texas Instruments Little Logic Application Report
CMOS Power Consumption and CPD Calculation (Rev. B)
LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)
Design Summary for WCSP Little Logic (Rev. B)
How to Select Little Logic (Rev. A)
Low-Voltage Logic (LVC) Designer's Guide
Selecting the Right Level Translation Solution (Rev. A)
TI IBIS File Creation, Validation, and Distribution Processes
Little Logic Guide 2018 (Rev. G)
Understanding Advanced Bus-Interface Products Design Guide
Use of the CMOS Unbuffered Inverter in Oscillator Circuits
SN74LVC16373A 16-Bit Transparent D-Type Latch With 3-State Outputs datasheet (Rev. B)
Input and Output Characteristics of Digital Integrated Circuits
Signal Switch Data Book (Rev. A)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
Standard Linear & Logic for PCs, Servers & Motherboards
LOGIC Pocket Data Book (Rev. B)
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
Power-Up Behavior of Clocked Devices (Rev. B)
16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
SN74LVC16373ADLR | Datasheet
    SN74LVC16373ADLR | Texas Instruments | Zenode.ai