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FCBGA (CZH)

TMS320C6654CZHA8

Active
Texas Instruments

HIGH PERFORMANCE SINGLE-CORE C66X FIXED AND FLOATING-POINT DSP- UP TO 850MHZ

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FCBGA (CZH)

TMS320C6654CZHA8

Active
Texas Instruments

HIGH PERFORMANCE SINGLE-CORE C66X FIXED AND FLOATING-POINT DSP- UP TO 850MHZ

Find alt

Description

General part information

TMS320 Series

The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B, TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.(1)

Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic.

Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices.

Technical Specifications

Parameters and characteristics for this part

SpecificationTMS320C6654CZHA8
Clock Rate (Frequency)850 MHz
InterfaceUART, PCIe, DDR3, I2C, SPI, EBI/EMI, McBSP, Ethernet, UPP
Mounting TypeSurface Mount
Non-Volatile Memory Size128 kB
Non-Volatile Memory TypeROM
On-Chip RAM1.06 MB
Operating Temperature (Max)100 °C
Operating Temperature (Min)-40 °C
Package / CaseFCBGA, 625-BFBGA
Package Length21 mm
Package Name625-FCBGA
Package Width21 mm
TypeFixed/Floating Point
Voltage - CoreVariable
Voltage - I/O (Option 1)1 V
Voltage - I/O (Option 2)1.5 V
Voltage - I/O (Option 3)1.8 V

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

Thermal Design Guide for DSP and Arm Application Processors (Rev. B)
Hardware Design Guide for KeyStone Devices (Rev. D)
KeyStone I DDR3 interface bring-up
PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)
AN-1281 Bumped Die (Flip Chip) Packages (Rev. A)
TMS320C66x high-performance multicore DSPs for video surveillance
SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)
Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)
TI DSP Benchmarking
Plastic Ball Grid Array [PBGA] Application Note (Rev. B)
Leveraging multicore processors for machine vision applications
TMS320C6652/54/55/57 Multicore Fixed and Floating-Point DSP SR1.0 (Rev. C)
Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG
Universal Parallel Port (uPP) for KeyStone Architecture User's Guide
C66x DSP Cache User's Guide
External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)
KeyStone Multicore SoC Tool Suite: one platform for all needs
TMS320C6657/55/54 Power efficient high performance for process-intensive apps (Rev. A)
Ethernet Media Access Controller (EMAC) User's Guide for KeyStone Devices
Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A)
DDR3 Design Requirements for KeyStone Devices (Rev. D)
Debug and Trace for KeyStone I Devices User's Guide (Rev. A)
Software and Hardware Design Challenges Due to Dynamic Raw NAND Market
64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)
Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)
Clocking Design Guide for KeyStone Devices
Multichannel Buffered Serial Port (MCBSP) User's Guide for KeyStone Devices
TI’s processors leading the way in embedded analytics
SERDES Link Commissioning on KeyStone I and II Devices
Accelerating high-performance computing development with Desktop Linux SDK
Flip Chip Ball Grid Array Package Reference Guide (Rev. A)
KeyStone I DDR3 Initialization (Rev. E)
How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)
KeyStone Memory Architecture White Paper (Rev. A)
DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)
DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E)
Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide
General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide
Using DSPLIB FFT Implementation for Real Input and Without Data Scaling
Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)
System Analyzer User's Guide (Rev. F)
TMS320C66x DSP Generation of Devices (Rev. A)
TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor datasheet (Rev. E)
C66x CPU and Instruction Set Reference Guide
Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)
Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)
SerDes Implementation Guidelines for KeyStone I Devices
TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U)
C66x CorePac User's Guide (Rev. C)
Optimizing Loops on the C66x DSP
OpenMP Programming for TMS320C66x Multicore DSPs (Rev. A)
Keystone Bootloader Resources and FAQ
Superior performance at breakthrough size, weight & power
Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)
TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W)
Keystone Error Detection and Correction EDC ECC (Rev. A)
Keystone Multicore Device Family Schematic Checklist
TI Keystone DSP PCIe SerDes IBIS-AMI Models
KeyStone Lab Manual - Training
PCIe Use Cases for KeyStone Devices
Introduction to TMS320C6000 DSP Optimization
Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)
SYS/BIOS(TI-RTOS Kernel) USer Guide