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TSSOP (PW)

SN74LVC74APWR

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Texas Instruments

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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TSSOP (PW)

SN74LVC74APWR

Active
Texas Instruments

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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Description

General part information

74LVC74 Series

The SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as a translator in a mixed 3.3 V/5 V system environment.

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVC74APWR
Clock Frequency150 MHz
Current - Output High24 mA
Current - Output Low24 mA
Current - Quiescent (Iq)10 µA
FunctionSet(Preset) and Reset
Input Capacitance5 pF
Max CL50 pF
Max Propagation Delay5.2 ns
Mounting TypeSurface Mount
Number of Bits per Element1 bits
Number of Elements2
Operating Temperature (Max)125 °C
Operating Temperature (Min)-40 °C
Output TypeComplementary
Package Length0.173 in
Package Name14-TSSOP
Package Width4.4 mm
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply (Maximum)3.6 V
Voltage - Supply (Minimum)1.65 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)
Low-Voltage Logic (LVC) Designer's Guide
Use of the CMOS Unbuffered Inverter in Oscillator Circuits
Little Logic Guide 2018 (Rev. G)
Input and Output Characteristics of Digital Integrated Circuits
Design Summary for WCSP Little Logic (Rev. B)
Understanding Advanced Bus-Interface Products Design Guide
SNx4LVC74A Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset datasheet (Rev. W)
How to Select Little Logic (Rev. A)
Selecting the Right Level Translation Solution (Rev. A)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Standard Linear & Logic for PCs, Servers & Motherboards
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
Texas Instruments Little Logic Application Report
16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
Live Insertion
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
Power-Up Behavior of Clocked Devices (Rev. B)
TI IBIS File Creation, Validation, and Distribution Processes
Signal Switch Data Book (Rev. A)
LVC Characterization Information
Logic Guide (Rev. AB)
STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS
LOGIC Pocket Data Book (Rev. B)
Implications of Slow or Floating CMOS Inputs (Rev. E)
CMOS Power Consumption and CPD Calculation (Rev. B)
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)