74LVC74 Series

Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset

Catalog

Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset

Part	Number of Bits per Element	Package Name	Operating Temperature (Max)	Operating Temperature (Min)	Trigger Type	Mounting Type	Current - Output Low	Current - Output High	Package Width	Package Length	Current - Quiescent (Iq)	Qualification	Function	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Type	Grade	Output Type	Max Propagation Delay	Max CL	Clock Frequency	Number of Elements	Input Capacitance
Texas Instruments SN74LVC74AQPWRQ1	1 bits	14-TSSOP	125 °C	-40 °C	Positive Edge	Surface Mount	24 mA	24 mA	4.4 mm	0.173 in	10 µA	AEC-Q100	Set(Preset) and Reset	3.6 V	2 V	D-Type	Automotive	Complementary	5.2 ns	50 pF	150 MHz	2	5 pF
Texas Instruments SN74LVC74AQPWREP	1 bits	14-TSSOP	125 °C	-40 °C	Positive Edge	Surface Mount	24 mA	24 mA	4.4 mm	0.173 in	10 µA		Set(Preset) and Reset	3.6 V	2 V	D-Type		Complementary	5.2 ns	50 pF	150 MHz	2	5 pF
Texas Instruments SN74LVC74ADBR	1 bits	14-SSOP	125 °C	-40 °C	Positive Edge	Surface Mount	24 mA	24 mA	5.3 mm	0.209 in	10 µA		Set(Preset) and Reset	3.6 V	1.65 V	D-Type		Complementary	5.2 ns	50 pF	150 MHz	2	5 pF
Texas Instruments SN74LVC74APWG4	1 bits	14-TSSOP	125 °C	-40 °C	Positive Edge	Surface Mount	24 mA	24 mA	4.4 mm	0.173 in	10 µA		Set(Preset) and Reset	3.6 V	1.65 V	D-Type		Complementary	5.2 ns	50 pF	150 MHz	2	5 pF
Texas Instruments SN74LVC74ANS	1 bits	14-SO 14-SOIC	125 °C	-40 °C	Positive Edge	Surface Mount	24 mA	24 mA	5.3 mm	0.209 in	10 µA		Set(Preset) and Reset	3.6 V	1.65 V	D-Type		Complementary	5.2 ns 5.4 ns	50 pF	150 MHz	2	5 pF
Texas Instruments SN74LVC74ADT	1 bits	14-SOIC	125 °C	-40 °C	Positive Edge	Surface Mount	24 mA	24 mA	3.9 mm	0.154 in	10 µA		Set(Preset) and Reset	3.6 V	1.65 V	D-Type		Complementary	5.2 ns	50 pF	150 MHz	2	5 pF
Texas Instruments SN74LVC74ADRE4	1 bits	14-SOIC	125 °C	-40 °C	Positive Edge	Surface Mount	24 mA	24 mA	3.9 mm	0.154 in	10 µA		Set(Preset) and Reset	3.6 V	1.65 V	D-Type		Complementary	5.2 ns	50 pF	150 MHz	2	5 pF
Texas Instruments SN74LVC74AD	1 bits	14-SOIC	125 °C	-40 °C	Positive Edge	Surface Mount	24 mA	24 mA	3.9 mm	0.154 in	10 µA		Set(Preset) and Reset	3.6 V	1.65 V	D-Type		Complementary	5.2 ns	50 pF	150 MHz	2	5 pF
Texas Instruments SN74LVC74AMDREP	1 bits	14-SOIC	125 °C	-55 °C	Positive Edge	Surface Mount	24 mA	24 mA	3.9 mm	0.154 in	10 µA		Set(Preset) and Reset	3.6 V	2 V	D-Type		Complementary	5.2 ns	50 pF	100 MHz	2	5 pF
Texas Instruments SN74LVC74ADBRG4	1 bits	14-SSOP	125 °C	-40 °C	Positive Edge	Surface Mount	24 mA	24 mA	5.3 mm	0.209 in	10 µA		Set(Preset) and Reset	3.6 V	1.65 V	D-Type		Complementary	5.2 ns	50 pF	150 MHz	2	5 pF

Catalog

Enhanced Product Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset

Description

The SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as a translator in a mixed 3.3 V/5 V system environment. The SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as a translator in a mixed 3.3 V/5 V system environment.