CD74HC112MT
ObsoleteTexas Instruments
HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
CD74HC112MT
ObsoleteTexas Instruments
HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
Description
General part information
74HC112 Series
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset
Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC112MT |
|---|---|
| Clock Frequency | 60 MHz |
| Current - Output High | 5.2 mA |
| Current - Output Low | 5.2 mA |
| Current - Quiescent (Iq) | 4 µA |
| Function | Set(Preset) and Reset |
| Input Capacitance | 10 pF |
| Max CL | 50 pF |
| Max Propagation Delay | 30 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 bits |
| Number of Elements | 2 |
| Operating Temperature (Max) | 125 °C |
| Operating Temperature (Min) | -55 °C |
| Output Type | Complementary |
| Package Length | 0.154 in |
| Package Name | 16-SOIC |
| Package Width | 3.9 mm |
| Trigger Type | Negative Edge |
| Type | JK Type |
| Voltage - Supply (Maximum) | 6 V |
| Voltage - Supply (Minimum) | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Sign in to see pricing
Create a free account to access distributor pricing data.
CAD
3D models and CAD resources for this part
Documents
Technical documentation and resources
Live Insertion
Input and Output Characteristics of Digital Integrated Circuits
Logic Guide (Rev. AB)
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Designing With Logic (Rev. C)
Signal Switch Data Book (Rev. A)
LOGIC Pocket Data Book (Rev. B)
TI IBIS File Creation, Validation, and Distribution Processes
Power-Up Behavior of Clocked Devices (Rev. B)
CMOS Power Consumption and CPD Calculation (Rev. B)
Implications of Slow or Floating CMOS Inputs (Rev. E)
CDx4HC112, CDx4HCT112 Dual J-K Flip-Flop with Set and Reset with Negative-Edge Trigger datasheet (Rev. J)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
SN54/74HCT CMOS Logic Family Applications and Restrictions
