CD74HC112 Series

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

Catalog

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

Part	Clock Frequency	Trigger Type	Output Type	Operating Temperature (Max)	Operating Temperature (Min)	Input Capacitance	Current - Quiescent (Iq)	Mounting Type	Number of Elements	Current - Output High	Current - Output Low	Package Name	Function	Max Propagation Delay	Max CL	Type	Number of Bits per Element	Package Width	Package Length	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)
Texas Instruments CD74HC112M96	60 MHz	Negative Edge	Complementary	125 °C	-55 °C	10 pF	4 µA	Surface Mount	2	5.2 mA	5.2 mA	16-SOIC	Set(Preset) and Reset	30 ns	50 pF	JK Type	1 bits	3.9 mm	0.154 in	2 V	6 V
Texas Instruments CD74HC112E	60 MHz	Negative Edge	Complementary	125 °C	-55 °C	10 pF	4 µA	Through Hole	2	5.2 mA	5.2 mA	16-DIP 16-PDIP	Set(Preset) and Reset	30 ns	50 pF	JK Type	1 bits	7.62 mm	0.3 in	2 V	6 V

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset