CD74ACT112M
ActiveDUAL NEGATIVE-EDGE TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
Deep-Dive with AI
Search across all available documentation for this part.
CD74ACT112M
ActiveDUAL NEGATIVE-EDGE TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CD74ACT112M |
|---|---|
| Clock Frequency | 100 MHz |
| Current - Output High, Low [custom] | 24 mA |
| Current - Output High, Low [custom] | 24 mA |
| Current - Quiescent (Iq) | 4 çA |
| Function | Reset, Set(Preset) |
| Input Capacitance | 10 pF |
| Max Propagation Delay @ V, Max CL | 10.3 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements [custom] | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 C |
| Output Type | Complementary |
| Package / Case | 16-SOIC |
| Package / Case | 3.9 mm Width, 0.154 in |
| Supplier Device Package | 16-SOIC |
| Trigger Type | Negative Edge |
| Type | JK Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
CD74ACT112 Series
Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset
| Part | Output Type | Max Propagation Delay @ V, Max CL | Type | Operating Temperature [Min] | Operating Temperature [Max] | Number of Bits per Element | Mounting Type | Clock Frequency | Number of Elements [custom] | Input Capacitance | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Function | Supplier Device Package | Package / Case | Package / Case | Current - Quiescent (Iq) | Voltage - Supply [Max] | Voltage - Supply [Min] | Trigger Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74ACT112MThe ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. | Complementary | 10.3 ns | JK Type | -55 C | 125 °C | 1 | Surface Mount | 100 MHz | 2 | 10 pF | 24 mA | 24 mA | Reset, Set(Preset) | 16-SOIC | 16-SOIC | 0.154 in, 3.9 mm Width | 4 çA | 5.5 V | 4.5 V | Negative Edge |
Description
General part information
CD74ACT112 Series
The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
Documents
Technical documentation and resources