CD74ACT112 Series
Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset
| Part | Output Type | Max Propagation Delay @ V, Max CL | Type | Operating Temperature [Min] | Operating Temperature [Max] | Number of Bits per Element | Mounting Type | Clock Frequency | Number of Elements [custom] | Input Capacitance | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Function | Supplier Device Package | Package / Case | Package / Case | Current - Quiescent (Iq) | Voltage - Supply [Max] | Voltage - Supply [Min] | Trigger Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74ACT112M | Complementary | 10.3 ns | JK Type | -55 C | 125 °C | 1 | Surface Mount | 100 MHz | 2 | 10 pF | 24 mA | 24 mA | Reset, Set(Preset) | 16-SOIC | 16-SOIC | 0.154 in, 3.9 mm Width | 4 çA | 5.5 V | 4.5 V | Negative Edge |
Key Features
• Inputs Are TTL-Voltage CompatibleSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015Inputs Are TTL-Voltage CompatibleSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015
Description
AI
The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.