
S25FL128SAGBHIA03
ActiveNOR FLASH SERIAL (SPI, DUAL SPI, QUAD SPI) 3V/3.3V 128M-BIT 128M/64M/32M X 1/2-BIT/4-BIT 14.5NS 24-PIN BGA T/R
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S25FL128SAGBHIA03
ActiveNOR FLASH SERIAL (SPI, DUAL SPI, QUAD SPI) 3V/3.3V 128M-BIT 128M/64M/32M X 1/2-BIT/4-BIT 14.5NS 24-PIN BGA T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | S25FL128SAGBHIA03 |
|---|---|
| Clock Frequency | 133 MHz |
| Memory Format | FLASH |
| Memory Interface | SPI - Quad I/O |
| Memory Organization | 16M x 8 |
| Memory Size | 128 Mb |
| Memory Type | Non-Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 24-TBGA |
| Supplier Device Package | 24-BGA |
| Technology | FLASH - NOR |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 3.20 | |
| 10 | $ 2.98 | |||
| 25 | $ 2.89 | |||
| 50 | $ 2.83 | |||
| 100 | $ 2.76 | |||
| 250 | $ 2.67 | |||
| 500 | $ 2.61 | |||
| 1000 | $ 2.56 | |||
| Digi-Reel® | 1 | $ 3.20 | ||
| 10 | $ 2.98 | |||
| 25 | $ 2.89 | |||
| 50 | $ 2.83 | |||
| 100 | $ 2.76 | |||
| 250 | $ 2.67 | |||
| 500 | $ 2.61 | |||
| 1000 | $ 2.56 | |||
| Tape & Reel (TR) | 2500 | $ 2.53 | ||
| Newark | Each (Supplied on Cut Tape) | 1 | $ 4.73 | |
| 10 | $ 3.94 | |||
| 25 | $ 3.85 | |||
| 50 | $ 3.80 | |||
| 100 | $ 3.74 | |||
| 250 | $ 3.59 | |||
| 500 | $ 3.46 | |||
| 1000 | $ 3.34 | |||
Description
General part information
S25FL128 Series
S25FL128SAGBHIA03 is an SPI multi-I/O, 3.0V FL-S flash memory. It connects to a host system via a SPI. Traditional SPI single-bit serial input and output (Single I/O or SIO) is supported as well as optional two-bit (Dual I/O or DIO) and four-bit (Quad I/O or QIO) serial commands. This multiple-width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The Eclipse architecture features a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erasing than prior generation SPI programs or erase algorithms. It offers high densities coupled with the flexibility and fast performance required by a variety of embedded applications. It is ideal for code shadowing, XIP, and data storage.
Documents
Technical documentation and resources