S26KS512SDPBHV020 is a S26KS512S HYPERFLASH™ high-speed CMOS, MIRRORBIT™ NOR flash device with the HYPERBUS™ low signal count DDR interface, that achieves high speed read throughput. The DDR protocol transfers two data bytes per clock cycle on the data (DQ) signals. A read or write access for the HYPERFLASH™ consists of a series of 16-bit wide, one clock cycle data transfers at the internal HYPERFLASH™ core and two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. Command/address/write-data values are center aligned with the clock edges and read-data values are edge aligned with the transitions of RWDS. During linear operation accesses start at a selected location and continue in a sequential manner until the read operation is terminated, when CS# returns HIGH. Write transactions transfer one or more 16-bit values.