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74ALVCH16260 - Block Diagram

74ALVCH16260PAG

Obsolete
Renesas Electronics Corporation

3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS, BUS-HOLD

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74ALVCH16260 - Block Diagram

74ALVCH16260PAG

Obsolete
Renesas Electronics Corporation

3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS, BUS-HOLD

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Description

General part information

74ALVCH16260 Series

The 74ALVCH16260 12-bit to 24-bit multiplexed D-type latch is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory interleaving applications. The 74ALVCH16260 has "bus-hold" which prevents floating inputs and eliminates the need for pull-up/down resistors. The 74ALVCH16260 operates at -40C to +85C

Technical Specifications

Parameters and characteristics for this part

Specification74ALVCH16260PAG
Circuit12:24
Current - Output High24 mA
Current - Output Low24 mA
Delay Time - Propagation1 ns
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature (Max)85 °C
Operating Temperature (Min)-40 °C
Output TypeTri-State
Package Length0.24 in
Package Name56-TSSOP, 56-TFSOP
Package Width6.1 mm
Voltage - Supply (Maximum)3.6 V
Voltage - Supply (Minimum)2.3 V

Pricing

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