SN74HCT377DW

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Texas Instruments

OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

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DocumentsSN54HCT377, SN74HCT377 datasheet (Rev. D)

SN74HCT377DW

Active

Texas Instruments

OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

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DocumentsSN54HCT377, SN74HCT377 datasheet (Rev. D)

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics commom to parts in this series

Specification	SN74HCT377DW	74HCT377 Series

Clock Frequency	37 MHz	37 - 50 MHz
Current - Output High, Low	4 mA, 4 mA	4 mA
Current - Quiescent (Iq)	8 ÁA	8 ÁA
Function	Standard	Standard
Input Capacitance	3 pF	3 - 10 pF
Max Propagation Delay @ V, Max CL	28 ns	28 - 38 ns
Mounting Type	Surface Mount	Surface Mount, Through Hole
Number of Bits per Element	8	8
Number of Elements [custom]	1	1
Operating Temperature [Max]	85 °C	85 - 125 °C
Operating Temperature [Min]	-40 °C	-55 - -40 °C
Output Type	Non-Inverted	Non-Inverted
Package / Case	7.5 mm, 0.295 in	0.295 - 7.5 mm
Package / Case	20-SOIC	20-SOIC, 20-DIP
Package / Case	-	0.3 in
Package / Case	-	7.62 mm
Supplier Device Package	20-SOIC	20-SOIC, 20-PDIP
Trigger Type	Positive Edge	Positive Edge
Type	D-Type	D-Type
Voltage - Supply [Max]	5.5 V	5.5 V
Voltage - Supply [Min]	4.5 V	4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.51
		10	$ 1.35
		25	$ 1.28
		100	$ 1.05
		250	$ 0.98
Texas Instruments	TUBE	1	$ 1.30
		100	$ 0.88
		250	$ 0.68
		1000	$ 0.45

74HCT377 Series

OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

Part	Voltage - Supply [Max]	Voltage - Supply [Min]	Type	Input Capacitance	Trigger Type	Current - Output High, Low	Number of Bits per Element	Function	Mounting Type	Number of Elements [custom]	Max Propagation Delay @ V, Max CL	Package / Case	Package / Case	Clock Frequency	Supplier Device Package	Current - Quiescent (Iq)	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case
Texas Instruments SN74HCT377DW These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\. These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.	5.5 V	4.5 V	D-Type	3 pF	Positive Edge	4 mA, 4 mA	8	Standard	Surface Mount	1	28 ns	0.295 in, 7.5 mm	20-SOIC	37 MHz	20-SOIC	8 ÁA	Non-Inverted	85 °C	-40 °C
Texas Instruments SN74HCT377N These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\. These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.	5.5 V	4.5 V	D-Type	3 pF	Positive Edge	4 mA, 4 mA	8	Standard	Through Hole	1	28 ns		20-DIP	37 MHz	20-PDIP	8 ÁA	Non-Inverted	85 °C	-40 °C	0.3 in	7.62 mm
Texas Instruments CD74HCT377ME4 Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-SOIC (0.295", 7.50mm Width)	5.5 V	4.5 V	D-Type	10 pF	Positive Edge	4 mA, 4 mA	8	Standard	Surface Mount	1	38 ns	0.295 in, 7.5 mm	20-SOIC	50 MHz	20-SOIC	8 ÁA	Non-Inverted	125 °C	-55 C
Texas Instruments SN74HCT377DWR These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\. These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.	5.5 V	4.5 V	D-Type	3 pF	Positive Edge	4 mA, 4 mA	8	Standard	Surface Mount	1	28 ns	0.295 in, 7.5 mm	20-SOIC	37 MHz	20-SOIC	8 ÁA	Non-Inverted	85 °C	-40 °C
Texas Instruments CD74HCT377E The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low. The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low.	5.5 V	4.5 V	D-Type	10 pF	Positive Edge	4 mA, 4 mA	8	Standard	Through Hole	1	38 ns		20-DIP	50 MHz	20-PDIP	8 ÁA	Non-Inverted	125 °C	-55 C	0.3 in	7.62 mm
Texas Instruments CD74HCT377EG4 Flip Flop 1 Element D-Type 8 Bit Positive Edge 20-DIP (0.300", 7.62mm)	5.5 V	4.5 V	D-Type	10 pF	Positive Edge	4 mA, 4 mA	8	Standard	Through Hole	1	38 ns		20-DIP	50 MHz	20-PDIP	8 ÁA	Non-Inverted	125 °C	-55 C	0.3 in	7.62 mm
Texas Instruments CD74HCT377M The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low. The ’HC377 and ’HCT377 are octal D-type flip-flops with a buffered clock (CP) common to all eight flip-flops. All the flip-flops are loaded simultaneously on the positive edge of the clock (CP) when the Data Enable (E\) is Low.	5.5 V	4.5 V	D-Type	10 pF	Positive Edge	4 mA, 4 mA	8	Standard	Surface Mount	1	38 ns	0.295 in, 7.5 mm	20-SOIC	50 MHz	20-SOIC	8 ÁA	Non-Inverted	125 °C	-55 C

Description

General part information

74HCT377 Series

These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear.

Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.

These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear.

Documents

Technical documentation and resources

SN54HCT377, SN74HCT377 datasheet (Rev. D)

Data sheet