SN74HC164DRG3
Active8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Deep-Dive with AI
Search across all available documentation for this part.
SN74HC164DRG3
Active8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.57 | |
| 10 | $ 0.50 | |||
| 25 | $ 0.47 | |||
| 100 | $ 0.39 | |||
| 250 | $ 0.36 | |||
| 500 | $ 0.31 | |||
| 1000 | $ 0.24 | |||
| Digi-Reel® | 1 | $ 0.57 | ||
| 10 | $ 0.50 | |||
| 25 | $ 0.47 | |||
| 100 | $ 0.39 | |||
| 250 | $ 0.36 | |||
| 500 | $ 0.31 | |||
| 1000 | $ 0.24 | |||
| Tape & Reel (TR) | 2500 | $ 0.19 | ||
| Texas Instruments | LARGE T&R | 1 | $ 0.51 | |
| 100 | $ 0.34 | |||
| 250 | $ 0.27 | |||
| 1000 | $ 0.18 | |||
Description
General part information
SN74HC164 Series
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.
Documents
Technical documentation and resources