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SN74HC164 Series

8-Bit Parallel-Out Serial Shift Registers

Manufacturer: Texas Instruments

Catalog

8-Bit Parallel-Out Serial Shift Registers

Key Features

Wide Operating Voltage Range of 2 V to 6 VOutputs Can Drive Up to 10 LSTTL LoadsLow Power Consumption, 80-µA Maximum ICCTypical tpd= 20 ns±4-mA Output Drive at 5 VLow Input Current of 1-µA MaximumAND-Gated (Enable/Disable) Serial InputsFully Buffered Clock and Serial InputsDirect ClearOn Products Compliant to MIL-PRF-38535,All Parameters Are Tested Unless OtherwiseNoted. On All Other Products, ProductionProcessing Does Not Necessarily IncludeTesting of All Parameters.Wide Operating Voltage Range of 2 V to 6 VOutputs Can Drive Up to 10 LSTTL LoadsLow Power Consumption, 80-µA Maximum ICCTypical tpd= 20 ns±4-mA Output Drive at 5 VLow Input Current of 1-µA MaximumAND-Gated (Enable/Disable) Serial InputsFully Buffered Clock and Serial InputsDirect ClearOn Products Compliant to MIL-PRF-38535,All Parameters Are Tested Unless OtherwiseNoted. On All Other Products, ProductionProcessing Does Not Necessarily IncludeTesting of All Parameters.

Description

AI
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.