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SN74HC164 Series

8-Bit Parallel-Out Serial Shift Registers

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

8-Bit Parallel-Out Serial Shift Registers

PartLogic TypeNumber of Elements [custom]Mounting TypeOutput TypePackage / CasePackage / CasePackage / CaseNumber of Bits per ElementFunctionOperating Temperature [Max]Operating Temperature [Min]Voltage - Supply [Min]Voltage - Supply [Max]Package / Case [custom]Package / Case [custom]Supplier Device PackagePackage / Case [y]Package / Case [y]
Texas Instruments
SN74HC164DT
Shift Register
1
Surface Mount
Push-Pull
3.9 mm
0.154 in
14-SOIC
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
Texas Instruments
SN74HC164DRG4
Shift Register
1
Surface Mount
Push-Pull
3.9 mm
0.154 in
14-SOIC
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
Texas Instruments
SN74HC164D
Shift Register
1
Surface Mount
Push-Pull
3.9 mm
0.154 in
14-SOIC
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
Texas Instruments
SN74HC164DR
Shift Register
1
Surface Mount
Push-Pull
3.9 mm
0.154 in
14-SOIC
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
Texas Instruments
SN74HC164PW
Shift Register
1
Surface Mount
Push-Pull
14-TSSOP
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
0.173 in
4.4 mm
14-TSSOP
Texas Instruments
SN74HC164PWT
Shift Register
1
Surface Mount
Push-Pull
14-TSSOP
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
0.173 in
4.4 mm
14-TSSOP
Texas Instruments
SN74HC164DRG3
Shift Register
1
Surface Mount
Push-Pull
3.9 mm
0.154 in
14-SOIC
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
Texas Instruments
SN74HC164NSR
Shift Register
1
Surface Mount
Push-Pull
14-SOIC
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
14-SO
5.3 mm
0.209 in
Texas Instruments
SN74HC164N
Shift Register
1
Through Hole
Push-Pull
7.62 mm
0.3 in
14-DIP
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
Texas Instruments
SN74HC164PWRG4
Shift Register
1
Surface Mount
Push-Pull
14-TSSOP
8
Serial to Parallel
125 °C
-40 °C
2 V
6 V
0.173 in
4.4 mm
14-TSSOP

Key Features

Wide Operating Voltage Range of 2 V to 6 VOutputs Can Drive Up to 10 LSTTL LoadsLow Power Consumption, 80-µA Maximum ICCTypical tpd= 20 ns±4-mA Output Drive at 5 VLow Input Current of 1-µA MaximumAND-Gated (Enable/Disable) Serial InputsFully Buffered Clock and Serial InputsDirect ClearOn Products Compliant to MIL-PRF-38535,All Parameters Are Tested Unless OtherwiseNoted. On All Other Products, ProductionProcessing Does Not Necessarily IncludeTesting of All Parameters.Wide Operating Voltage Range of 2 V to 6 VOutputs Can Drive Up to 10 LSTTL LoadsLow Power Consumption, 80-µA Maximum ICCTypical tpd= 20 ns±4-mA Output Drive at 5 VLow Input Current of 1-µA MaximumAND-Gated (Enable/Disable) Serial InputsFully Buffered Clock and Serial InputsDirect ClearOn Products Compliant to MIL-PRF-38535,All Parameters Are Tested Unless OtherwiseNoted. On All Other Products, ProductionProcessing Does Not Necessarily IncludeTesting of All Parameters.

Description

AI
These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK. These 8-bit shift registers feature AND-gated serial inputs and an asynchronous clear (CLR) input. The gated serial (A and B) inputs permit complete control over incoming data; a low at either input inhibits entry of the new data and resets the first flip-flop to the low level at the next clock (CLK) pulse. A high-level input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can be changed while CLK is high or low, provided the minimum set-up time requirements are met. Clocking occurs on the low-to-high-level transition of CLK.