
S25FL512SAGBHIA13
ActiveFLASH MEMORY, SERIAL NOR, 512 MBIT, 64M X 8BIT, SPI, BGA, 24 PINS
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S25FL512SAGBHIA13
ActiveFLASH MEMORY, SERIAL NOR, 512 MBIT, 64M X 8BIT, SPI, BGA, 24 PINS
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Technical Specifications
Parameters and characteristics for this part
| Specification | S25FL512SAGBHIA13 |
|---|---|
| Clock Frequency | 133 MHz |
| Memory Format | FLASH |
| Memory Interface | SPI - Quad I/O |
| Memory Organization | 64 M |
| Memory Size | 64 MB |
| Memory Type | Non-Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 24-TBGA |
| Supplier Device Package | 24-BGA |
| Technology | FLASH - NOR |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 6.28 | |
| 10 | $ 5.85 | |||
| 25 | $ 5.67 | |||
| 50 | $ 5.54 | |||
| 100 | $ 5.40 | |||
| 250 | $ 5.23 | |||
| 500 | $ 5.14 | |||
| Digi-Reel® | 1 | $ 6.28 | ||
| 10 | $ 5.85 | |||
| 25 | $ 5.67 | |||
| 50 | $ 5.54 | |||
| 100 | $ 5.40 | |||
| 250 | $ 5.23 | |||
| 500 | $ 5.14 | |||
| Tape & Reel (TR) | 2500 | $ 4.94 | ||
| Newark | Each (Supplied on Cut Tape) | 1 | $ 10.50 | |
| 10 | $ 9.32 | |||
| 25 | $ 8.89 | |||
| 50 | $ 8.57 | |||
| 100 | $ 8.27 | |||
| 250 | $ 7.88 | |||
| 500 | $ 7.60 | |||
| 1000 | $ 7.33 | |||
Description
General part information
S25FL512 Series
S25FL512SAGBHIA13 is a S25FL series 3V, FL-S serial peripheral interface (SPI) flash memory IC using MIRRORBIT™ technology - that stores two data bits in each memory array transistor, eclipse architecture - that dramatically improves program and erase performance and 65-nm process lithography. In addition, the FL-S family adds support for double data rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The eclipse architecture features a page programming buffer that allows up to 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. It offers high densities coupled with the flexibility and fast performance required by a variety of embedded applications. It is ideal for code shadowing, XIP, and data storage.
Documents
Technical documentation and resources