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HLQFP (PYP)

TMS320C6713BPYP200

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Texas Instruments

C67X FLOATING-POINT DSP- UP TO 300MHZ, MCBSP, 16-BIT EMIFA

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HLQFP (PYP)

TMS320C6713BPYP200

Active
Texas Instruments

C67X FLOATING-POINT DSP- UP TO 300MHZ, MCBSP, 16-BIT EMIFA

Find alt

Description

General part information

TMS320 Series

The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B, TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.(1)

Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic.

Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices.

Technical Specifications

Parameters and characteristics for this part

SpecificationTMS320C6713BPYP200
Clock Rate (Frequency)200 MHz
InterfaceMcBSP, Host Interface, I2C, McASP
Mounting TypeSurface Mount
Non-Volatile Memory TypeExternal
On-Chip RAM264 kB
Operating Temperature (Max)90 °C
Operating Temperature (Min)0 °C
Package / Case208-LQFP Exposed Pad
Package Length28 mm
Package Name208-HLQFP
Package Width28 mm
TypeFloating Point
Voltage - Core1.2 V
Voltage - I/O3.3 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E)
TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller RG (Rev. C)
Introduction to TMS320C6000 DSP Optimization
TMS320C621x/671x EDMA Performance Data
TMS320C6713, TMS320C6713B DSPs Silicon Errata (Silicon Revisions 2.0, 1.1) (Rev. J)
Thermal Considerations for the DM64xx, DM64x, and C6000 Devices
TMS320C6000 EDMA IO Scheduling and Performance
TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B)
TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide (Rev. A)
TMS320C6000 DSP Multi-channel Audio Serial Port (McASP) Reference Guide (Rev. J)
TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C)
TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q)
TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A)
TMS320C6713B Floating-Point Digital Signal Processor datasheet (Rev. B)
TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D)
TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C)
How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)
TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B)
Migrating from TMS320C6211B/C6711/C6711B and C6713 to TMS320C6713B (Rev. H)
TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C)
TMS320C6711D, C6712D, C6713B Power Consumption Summary (Rev. A)
TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G)
TMS320C621x/TMS320C671x EDMA Architecture
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