TPS536C5RSLR
Active12-PHASE DIGITAL STEP-DOWN MULTIPHASE CONTROLLER WITH SVI3 AND PMBUS FOR AMD PLATFORM 48-VQFN -40 TO 105
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TPS536C5RSLR
Active12-PHASE DIGITAL STEP-DOWN MULTIPHASE CONTROLLER WITH SVI3 AND PMBUS FOR AMD PLATFORM 48-VQFN -40 TO 105
Technical Specifications
Parameters and characteristics for this part
| Specification | TPS536C5RSLR |
|---|---|
| Applications | Controller, AMD |
| Mounting Type | Surface Mount |
| Number of Outputs [custom] | 2 |
| Operating Temperature [Max] | 105 ░C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 48-VFQFN Exposed Pad |
| Supplier Device Package | 48-VQFN (6x6) |
| Voltage - Input [Max] | 17 V |
| Voltage - Input [Min] | 4.5 V |
| Voltage - Output [Max] | 5.5 V |
| Voltage - Output [Min] | 0.25 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
TPS536C5 Series
12-phase digital step-down multiphase controller with SVI3 and PMBus for AMD platform
| Part | Number of Outputs [custom] | Voltage - Output [Max] | Voltage - Output [Min] | Package / Case | Mounting Type | Voltage - Input [Min] | Voltage - Input [Max] | Applications | Supplier Device Package | Operating Temperature [Min] | Operating Temperature [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments TPS536C5RSLRThe TPS536C5 is a fully AMD SVI3 compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ smart power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCOREslew rate and voltage positioning round out the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS536C5 device if offered in a thermally enhanced 48-pin QFN packaged and is rated to operate from –40°C to 125°C.
The TPS536C5 is a fully AMD SVI3 compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ smart power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCOREslew rate and voltage positioning round out the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS536C5 device if offered in a thermally enhanced 48-pin QFN packaged and is rated to operate from –40°C to 125°C. | 2 | 5.5 V | 0.25 V | 48-VFQFN Exposed Pad | Surface Mount | 4.5 V | 17 V | AMD, Controller | 48-VQFN (6x6) | -40 °C | 105 ░C |
Description
General part information
TPS536C5 Series
The TPS536C5 is a fully AMD SVI3 compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ smart power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCOREslew rate and voltage positioning round out the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS536C5 device if offered in a thermally enhanced 48-pin QFN packaged and is rated to operate from –40°C to 125°C.
The TPS536C5 is a fully AMD SVI3 compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ smart power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCOREslew rate and voltage positioning round out the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
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