CDCLVP111HFG/EM
Active1:10 HIGH SPEED CLOCK BUFFER WITH SELECTABLE INPUT CLOCK DRIVER
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CDCLVP111HFG/EM
Active1:10 HIGH SPEED CLOCK BUFFER WITH SELECTABLE INPUT CLOCK DRIVER
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Technical Specifications
Parameters and characteristics for this part
| Specification | CDCLVP111HFG/EM |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 3.5 GHz |
| Input | LVPECL, SSTL, LVDS, CML |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output | LVPECL |
| Package / Case | 36-CFlatPack |
| Ratio - Input:Output [custom] | 1 |
| Ratio - Input:Output [custom] | 10 |
| Supplier Device Package | 36-CFP |
| Type | Multiplexer, Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 3.8 V |
| Voltage - Supply [Min] | -2.375 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 1326.73 | |
| 10 | $ 1255.65 | |||
| 100 | $ 1184.58 | |||
CDCLVP111-SP Series
1:10 high speed clock buffer with selectable input clock driver
| Part | Package / Case | Frequency - Max [Max] | Output | Mounting Type | Input | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Voltage - Supply [Max] | Voltage - Supply [Min] | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Operating Temperature [Min] | Operating Temperature [Max] | Supplier Device Package | Type | Number of Circuits |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVP111HFG/EM | 36-CFlatPack | 3.5 GHz | LVPECL | Surface Mount | CML, LVDS, LVPECL, SSTL | 1 | 10 | 3.8 V | -2.375 V | -55 °C | 125 °C | 36-CFP | Fanout Buffer (Distribution), Multiplexer | 1 |
Description
General part information
CDCLVP111-SP Series
The CDCLVP111-SP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SP can accept two clock sources into an input multiplexer. The CDCLVP111-SP is specifically designed for driving 50Ω transmission lines. When an output pin is not used, leaving the pin open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50Ω.
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin must be connected to CLK0 and bypassed to GND using a 10nF capacitor.
For high-speed performance, the differential mode is strongly recommended.
Documents
Technical documentation and resources