CDCLVP111-SP Series
1:10 high speed clock buffer with selectable input clock driver
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
1:10 high speed clock buffer with selectable input clock driver
| Part | Package / Case | Frequency - Max [Max] | Output | Mounting Type | Input | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Voltage - Supply [Max] | Voltage - Supply [Min] | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Operating Temperature [Min] | Operating Temperature [Max] | Supplier Device Package | Type | Number of Circuits |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVP111HFG/EM | 36-CFlatPack | 3.5 GHz | LVPECL | Surface Mount | CML, LVDS, LVPECL, SSTL | 1 | 10 | 3.8 V | -2.375 V | -55 °C | 125 °C | 36-CFP | Fanout Buffer (Distribution), Multiplexer | 1 |
Key Features
• Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECLFully Compatible With LVECL and LVPECLSupports a Wide Supply Voltage Range From 2.375V to 3.8VSelectable Clock Input Through CLK_SELLow-Output Skew (Typical 15ps) for Clock-Distribution ApplicationsAdditive Jitter Less Than 1psPropagation Delay Less Than 355psOpen Input Default StateLVDS, CML, SSTL input CompatibleVBB Reference Voltage Output for Single-Ended ClockingFrequency Range From DC to 3.5GHzSupports Defense, Aerospace, and Medical ApplicationsControlled BaselineOne Assembly and Test SiteOne Fabrication SiteAvailable in Military (–55°C to 125°C) Temperature Range(1)Extended Product Life CycleExtended Product-Change NotificationProduct Traceability(1)Custom temperature ranges available.Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECLFully Compatible With LVECL and LVPECLSupports a Wide Supply Voltage Range From 2.375V to 3.8VSelectable Clock Input Through CLK_SELLow-Output Skew (Typical 15ps) for Clock-Distribution ApplicationsAdditive Jitter Less Than 1psPropagation Delay Less Than 355psOpen Input Default StateLVDS, CML, SSTL input CompatibleVBB Reference Voltage Output for Single-Ended ClockingFrequency Range From DC to 3.5GHzSupports Defense, Aerospace, and Medical ApplicationsControlled BaselineOne Assembly and Test SiteOne Fabrication SiteAvailable in Military (–55°C to 125°C) Temperature Range(1)Extended Product Life CycleExtended Product-Change NotificationProduct Traceability(1)Custom temperature ranges available.
Description
AI
The CDCLVP111-SP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SP can accept two clock sources into an input multiplexer. The CDCLVP111-SP is specifically designed for driving 50Ω transmission lines. When an output pin is not used, leaving the pin open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50Ω.
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin must be connected to CLK0 and bypassed to GND using a 10nF capacitor.
For high-speed performance, the differential mode is strongly recommended.
The CDCLVP111-SP is characterized for operation from –55°C to 125°C.
The CDCLVP111-SP clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111-SP can accept two clock sources into an input multiplexer. The CDCLVP111-SP is specifically designed for driving 50Ω transmission lines. When an output pin is not used, leaving the pin open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50Ω.
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin must be connected to CLK0 and bypassed to GND using a 10nF capacitor.
For high-speed performance, the differential mode is strongly recommended.
The CDCLVP111-SP is characterized for operation from –55°C to 125°C.