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FCCSP (CBD)

DRA712BGGCBDQ1

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Texas Instruments

600 MHZ ARM CORTEX-A15 SOC PROCESSOR WITH GRAPHICS & DUAL ARM CORTEX-M4 FOR INFOTAINMENT & CLUSTER

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FCCSP (CBD)

DRA712BGGCBDQ1

Active
Texas Instruments

600 MHZ ARM CORTEX-A15 SOC PROCESSOR WITH GRAPHICS & DUAL ARM CORTEX-M4 FOR INFOTAINMENT & CLUSTER

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Description

General part information

DRA712 Series

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Technical Specifications

Parameters and characteristics for this part

SpecificationDRA712BGGCBDQ1
Additional InterfacesMcSPI, SPI, IrDA, MMC/SD/SDIO, UART/USART, I2C, Ethernet, 1-Wire®, USB, DMA, CANbus, McASP
Bus Width32 Bit
Co-Processors/DSPIVA, BB2D, ARM® Cortex®-M4, GPU
Core ProcessorARM® Cortex®-A15
Display & Interface ControllersHDMI, LCD
Ethernet Ports (1Gbps)2
Ethernet Speed Options10/100/1000Mbps, 1Gbps
GradeAutomotive
Graphics AccelerationYes
Mounting TypeSurface Mount
Number of Cores1 Core
Operating Temperature (Max)125 °C
Operating Temperature (Min)-40 °C
Package / CaseFCBGA, 538-LFBGA
Package Length17 mm
Package Name538-FCBGA
Package Width17 mm
QualificationAEC-Q100
RAM ControllersDDR3, DDR3L
Security FeaturesDebug Security, Isolation Firewalls, Device Identity, Secure Boot, Secure Storage, Software IP Protection, Cryptography
Speed400 MHz
USBUSB 3.0, USB 2.0
USB 2.0 Count2 count
USB 3.0 Count1 count
Voltage - I/O (Option 1)1.35 V
Voltage - I/O (Option 2)1.5 V
Voltage - I/O (Option 3)1.8 V
Voltage - I/O (Option 4)3.3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices
Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC
A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B)
Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A)
Linux Boot Time Optimizations on DRA7xx Devices
Informational ADAS as Software Upgrade to Today’s Infotainment Systems
Tools and Techniques to Root Case Failures in Video Capture Subsystem
DRA72x and DRA71x SoC for Automotive Infortainment Silicon Errata (Rev. F)
Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A)
Today’s high-end infotainment soon becoming mainstream
Tools and Techniques for Audio Debugging
The Implementation of YUV422 Output for SRV
DRA71x Cost Effective Automotive Reference Design
AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E)
Jump Start Upgrading Your Digital Cluster Design with Jacinto 6 Platform (Rev. A)
IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC
Debugging Tools and Techniques With IPC3.x
Early Splash Screen on DRA7x Devices
Jacinto6 Android Video Encoder Software Design Specification User's Guide
MMC DLL Tuning (Rev. B)
DRA71x EVM CPU board user's guide (Rev. B)
Android Boot Optimization on DRA7xx Devices (Rev. A)
Optimization of GPU-Based Surround View on TI’s TDA2x SoC
Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device
Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B)
Jacinto6 Spread Spectrum Clocking Configuration (Rev. A)
Jacinto6 Android Video Decoder Software Design Specification User's Guide
Flashing Binaries to DRA7xx Factory Boards Using DFU
DRA71x Infotainment Applications Processor datasheet (Rev. G)
DRA74x_75x/DRA72x Performance (Rev. A)
DRA71x and DRA72x Technical Reference Manual (Rev. D)
Sharing VPE Between VISIONSDK and PSDKLA
Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices
Integrating AUTOSAR on TI SoC: Fundamentals
Gstreamer Migration Guidelines
Robust Rear-View Camera (RVC) App Report
Integrating New Cameras With Video Input Port on DRA7xx SoCs
Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A)
ECC/EDC on TDAxx (Rev. B)
Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A)
Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices
Achieving Early CAN Response on DRA7xx Devices
DRA712BGGCBDQ1 | Datasheet