Technical Specifications
Parameters and characteristics commom to parts in this series
Specification | SY89872UMG | SY89872 Series |
---|---|---|
- | - | |
Differential - Input:Output [custom] | True | True |
Differential - Input:Output [custom] | True | True |
Frequency - Max [Max] | 2 GHz | 2 GHz |
Input | LVPECL, HSTL, CML, LVDS | LVPECL, HSTL, CML, LVDS |
Mounting Type | Surface Mount | Surface Mount |
Number of Circuits | 1 | 1 |
Operating Temperature [Max] | 85 °C | 85 °C |
Operating Temperature [Min] | -40 °C | -40 °C |
Output | LVDS | LVDS |
Package / Case | 16-MLF®, 16-VFQFN Exposed Pad | 16-MLF®, 16-VFQFN Exposed Pad |
Ratio - Input:Output [custom] | 1:3 | 1:3 |
Type | Divider, Fanout Buffer (Distribution) | Divider, Fanout Buffer (Distribution) |
Voltage - Supply [Max] | 2.625 V | 2.625 V |
Voltage - Supply [Min] | 2.375 V | 2.375 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Distributor | Package | Quantity | $ | |
---|---|---|---|---|
Digikey | Tube | 1 | $ 13.40 | |
25 | $ 11.15 | |||
100 | $ 10.15 | |||
Microchip Direct | TUBE | 1 | $ 13.40 | |
25 | $ 11.15 | |||
100 | $ 10.15 | |||
1000 | $ 8.46 | |||
5000 | $ 7.81 | |||
10000 | $ 7.26 |
SY89872 Series
IC CLK BUFFER 1:3 2GHZ 16MLF
Part | Voltage - Supply [Min] | Voltage - Supply [Max] | Ratio - Input:Output [custom] | Number of Circuits | Package / Case | Type | Output | Input | Frequency - Max [Max] | Operating Temperature [Max] | Operating Temperature [Min] | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Mounting Type |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Microchip Technology SY89872UMI | 2.375 V | 2.625 V | 1:3 | 1 | 16-MLF®, 16-VFQFN Exposed Pad | Divider, Fanout Buffer (Distribution) | LVDS | CML, HSTL, LVDS, LVPECL | 2 GHz | 85 °C | -40 °C | Surface Mount | ||
Microchip Technology SY89872UMG | ||||||||||||||
Microchip Technology SY89872UMG | ||||||||||||||
Microchip Technology SY89872UMG | 2.375 V | 2.625 V | 1:3 | 1 | 16-MLF®, 16-VFQFN Exposed Pad | Divider, Fanout Buffer (Distribution) | LVDS | CML, HSTL, LVDS, LVPECL | 2 GHz | 85 °C | -40 °C | Surface Mount | ||
Microchip Technology SY89872UMI-TR | 2.375 V | 2.625 V | 1:3 | 1 | 16-MLF®, 16-VFQFN Exposed Pad | Divider, Fanout Buffer (Distribution) | LVDS | CML, HSTL, LVDS, LVPECL | 2 GHz | 85 °C | -40 °C | Surface Mount |
Description
General part information
SY89872 Series
This 2.5V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89872U includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank.Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF- AC reference is included for AC-coupled applications.The SY89872U is part of Micrel's high-speed Precision Edge® timing and distribution family. For 3.3V applications, consider the SY89873L. For applications that require an LVPECL output, consider the SY89872U.The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN).Guaranteed AC performance over temperature and voltage: >2GHz fMAX <750ps tPD (matched delay between banks) <15ps within-device skew <200ps rise/fall time Low jitter design 265 RMS phase jitter Unique input termination and VTpin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) Precision differential LVDS outputs Matched delay: all outputs have matched delay, independent of divider setting TTL/CMOS inputs for select and reset/disable Two output banks (matched delay) Bank A: Buffered copy of input clock (undivided) Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies 2.5V power supply Wide operating temperature range: -40°C to +85°C Available in 16-pin (3mm x 3mm) QFN package