
CY74FCT823BTPC
ObsoleteIC FF D-TYPE SNGL 9BIT 24DIP

CY74FCT823BTPC
ObsoleteIC FF D-TYPE SNGL 9BIT 24DIP
Description
General part information
74FCT823 Series
This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN\) and clear (CLR\) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH.
This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Technical Specifications
Parameters and characteristics for this part
| Specification | CY74FCT823BTPC |
|---|---|
| Current - Output High | 32 mA |
| Current - Output Low | 64 mA |
| Current - Quiescent (Iq) | 200 µA |
| Function | Master Reset |
| Input Capacitance | 5 pF |
| Max CL | 300 pF |
| Max Propagation Delay | 15 ns |
| Mounting Type | Through Hole |
| Number of Bits per Element | 9 bits |
| Number of Elements | 1 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package Length | 0.3 in |
| Package Name | 24-PDIP, 24-DIP |
| Package Width | 7.62 mm |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply (Maximum) | 5.25 V |
| Voltage - Supply (Minimum) | 4.75 V |
Pricing
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