V62/04703-01YE
ActiveTexas Instruments
ENHANCED PRODUCT DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS
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V62/04703-01YE
ActiveTexas Instruments
ENHANCED PRODUCT DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS
Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | V62/04703-01YE | CD74HC4017-EP Series |
|---|---|---|
| Count Rate | 60 MHz | 35 - 60 MHz |
| Direction | Up | Up |
| Logic Type | Decade, Counter | Decade, Counter |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Bits per Element | 5 | 5 - 10 |
| Number of Elements [custom] | 1 | 1 |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -40 °C | -40 °C |
| Package / Case | 16-TSSOP | 16-TSSOP, 16-SOIC |
| Package / Case | - | 0.154 - 3.9 mm Width |
| Package / Case [x] | 0.173 " | 0.173 " |
| Package / Case [x] | 4.4 mm | 4.4 mm |
| Reset | Asynchronous | Asynchronous |
| Supplier Device Package | 16-TSSOP | 16-TSSOP, 16-SOIC |
| Timing | - | Synchronous |
| Trigger Type | Negative, Positive | Negative, Positive |
| Voltage - Supply [Max] | 6 V | 6 V |
| Voltage - Supply [Min] | 2 V | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
CD74HC4017-EP Series
Enhanced Product Decade Counter/Divider With 10 Decoded Outputs
| Part | Reset | Logic Type | Operating Temperature [Min] | Operating Temperature [Max] | Trigger Type | Direction | Supplier Device Package | Voltage - Supply [Max] | Voltage - Supply [Min] | Mounting Type | Number of Elements [custom] | Package / Case [x] | Package / Case | Package / Case [x] | Count Rate | Number of Bits per Element | Package / Case | Timing |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments V62/04703-01YEThe CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads. | Asynchronous | Counter, Decade | -40 °C | 125 °C | Negative, Positive | Up | 16-TSSOP | 6 V | 2 V | Surface Mount | 1 | 0.173 " | 16-TSSOP | 4.4 mm | 60 MHz | 5 | ||
Texas Instruments CD74HC4017QM96EPThe CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads. | Asynchronous | Counter, Decade | -40 °C | 125 °C | Negative, Positive | Up | 16-SOIC | 6 V | 2 V | Surface Mount | 1 | 16-SOIC | 35 MHz | 10 | 0.154 in, 3.9 mm Width | Synchronous | ||
Texas Instruments V62/04703-01XEThe CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads. | Asynchronous | Counter, Decade | -40 °C | 125 °C | Negative, Positive | Up | 16-SOIC | 6 V | 2 V | Surface Mount | 1 | 16-SOIC | 60 MHz | 5 | 0.154 in, 3.9 mm Width | |||
Texas Instruments CD74HC4017QPWREPThe CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads. | Asynchronous | Counter, Decade | -40 °C | 125 °C | Negative, Positive | Up | 16-TSSOP | 6 V | 2 V | Surface Mount | 1 | 0.173 " | 16-TSSOP | 4.4 mm | 35 MHz | 10 | Synchronous |
Description
General part information
CD74HC4017-EP Series
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
Documents
Technical documentation and resources