CD74HC4017-EP Series

Enhanced Product Decade Counter/Divider With 10 Decoded Outputs

Link to Manufacturer Page: https://www.ti.com/

Catalog

Enhanced Product Decade Counter/Divider With 10 Decoded Outputs

Part	Reset	Logic Type	Operating Temperature [Min]	Operating Temperature [Max]	Trigger Type	Direction	Supplier Device Package	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Number of Elements [custom]	Package / Case [x]	Package / Case	Package / Case [x]	Count Rate	Number of Bits per Element	Package / Case	Timing
Texas Instruments V62/04703-01YE	Asynchronous	Counter, Decade	-40 °C	125 °C	Negative, Positive	Up	16-TSSOP	6 V	2 V	Surface Mount	1	0.173 "	16-TSSOP	4.4 mm	60 MHz	5
Texas Instruments CD74HC4017QM96EP	Asynchronous	Counter, Decade	-40 °C	125 °C	Negative, Positive	Up	16-SOIC	6 V	2 V	Surface Mount	1		16-SOIC		35 MHz	10	0.154 in, 3.9 mm Width	Synchronous
Texas Instruments V62/04703-01XE	Asynchronous	Counter, Decade	-40 °C	125 °C	Negative, Positive	Up	16-SOIC	6 V	2 V	Surface Mount	1		16-SOIC		60 MHz	5	0.154 in, 3.9 mm Width
Texas Instruments CD74HC4017QPWREP	Asynchronous	Counter, Decade	-40 °C	125 °C	Negative, Positive	Up	16-TSSOP	6 V	2 V	Surface Mount	1	0.173 "	16-TSSOP	4.4 mm	35 MHz	10		Synchronous

Key Features

• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of –40°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification PedigreeFully Static OperationBuffered InputsCommon ResetPositive Edge ClockingTypical fmax= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . 10 LSTTL LoadsBus Driver Outputs . . . 15 LSTTL LoadsBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsVCCVoltage = 2 V to 6 VHigh Noise Immunity NILor NIH= 30% of VCC, VCC= 5 VComponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of –40°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification PedigreeFully Static OperationBuffered InputsCommon ResetPositive Edge ClockingTypical fmax= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . 10 LSTTL LoadsBus Driver Outputs . . . 15 LSTTL LoadsBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsVCCVoltage = 2 V to 6 VHigh Noise Immunity NILor NIH= 30% of VCC, VCC= 5 VComponent qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Description

The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low. The device can drive up to ten low-power Schottky equivalent loads. The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low and can be used in conjunction with the clock enable (CE)\ input to cascade several stages. CE\ disables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low. The device can drive up to ten low-power Schottky equivalent loads.