SN65LVDS104DR

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Texas Instruments

1:4 LVDS CLOCK FANOUT BUFFER

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SN65LVDS104DR

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Texas Instruments

1:4 LVDS CLOCK FANOUT BUFFER

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Description Specifications Series Pricing CAD Documents

Description

General part information

65LVDS104 Series

The SN65LVDS10x are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644 is a data signaling technique that offers low-power, low-noise coupling, and switching speeds to transmit data at relatively long distances. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.

The SN65LVDS10x are characterized for operation from –40°C to 85°C.

Technical Specifications

Parameters and characteristics for this part

Specification	SN65LVDS104DR

Capacitance - Input	3 pF
Channel Configuration	1:4
Current - Supply	23 mA
Data Rate (Max)	400 Mbps
Delay Time	3.1 ns
Input	LVDS
Mounting Type	Surface Mount
Number of Channels	1
Operating Temperature (Max)	85 °C
Operating Temperature (Min)	-40 °C
Output	LVDS
Package Length	0.154 in
Package Name	16-SOIC
Package Width	3.9 mm
Type	Buffer, Multiplexer
Voltage - Supply (Maximum)	3.6 V
Voltage - Supply (Minimum)	3 V

65LVDS104 Series

1:4 LVDS clock fanout buffer

Part	Package Length	Package Name	Package Width	Output	Current - Supply	Mounting Type	Capacitance - Input	Channel Configuration	Number of Channels	Input	Data Rate (Max)	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)	Delay Time	Type	Operating Temperature (Min)	Operating Temperature (Max)
Texas Instruments SN65LVDS104PWRG4	0.173 in	16-TSSOP	4.4 mm	LVDS	23 mA	Surface Mount	3 pF	1:4	1	LVDS	400 Mbps	3.6 V	3 V	3.1 ns	Buffer Multiplexer	-40 °C	85 °C
Texas Instruments SN65LVDS104D	0.154 in	16-SOIC	3.9 mm	LVDS	23 mA	Surface Mount	3 pF	1:4	1	LVDS	400 Mbps	3.6 V	3 V	3.1 ns	Buffer Multiplexer	-40 °C	85 °C
Texas Instruments SN65LVDS104PWG4	0.173 in	16-TSSOP	4.4 mm	LVDS	23 mA	Surface Mount	3 pF	1:4	1	LVDS	400 Mbps	3.6 V	3 V	3.1 ns	Buffer Multiplexer	-40 °C	85 °C
Texas Instruments SN65LVDS104DG4	0.154 in	16-SOIC	3.9 mm	LVDS	23 mA	Surface Mount	3 pF	1:4	1	LVDS	400 Mbps	3.6 V	3 V	3.1 ns	Buffer Multiplexer	-40 °C	85 °C
Texas Instruments SN65LVDS104DRG4	0.154 in	16-SOIC	3.9 mm	LVDS	23 mA	Surface Mount	3 pF	1:4	1	LVDS	400 Mbps	3.6 V	3 V	3.1 ns	Buffer Multiplexer	-40 °C	85 °C
Texas Instruments SN65LVDS104PW	0.173 in	16-TSSOP	4.4 mm	LVDS	23 mA	Surface Mount	3 pF	1:4	1	LVDS	400 Mbps	3.6 V	3 V	3.1 ns	Buffer Multiplexer	-40 °C	85 °C
Texas Instruments SN65LVDS104PWR	0.173 in	16-TSSOP	4.4 mm	LVDS	23 mA	Surface Mount	3 pF	1:4	1	LVDS	400 Mbps	3.6 V	3 V	3.1 ns	Buffer Multiplexer	-40 °C	85 °C
Texas Instruments SN65LVDS104DR	0.154 in	16-SOIC	3.9 mm	LVDS	23 mA	Surface Mount	3 pF	1:4	1	LVDS	400 Mbps	3.6 V	3 V	3.1 ns	Buffer Multiplexer	-40 °C	85 °C

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

Datasheet

AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)

DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML