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VSSOP (DCU)

SN74LVC2G74MDCUTEP

Active
Texas Instruments

ENHANCED PRODUCT SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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VSSOP (DCU)

SN74LVC2G74MDCUTEP

Active
Texas Instruments

ENHANCED PRODUCT SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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Description

General part information

SN74LVC2G74-EP Series

This single positive edge triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial power down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVC2G74MDCUTEP
Clock Frequency200 MHz
Current - Output High24 mA
Current - Output Low24 mA
Current - Quiescent (Iq)10 µA
FunctionSet(Preset) and Reset
Input Capacitance5 pF
Max CL50 pF
Max Propagation Delay6.4 ns
Mounting TypeSurface Mount
Number of Bits per Element1 bits
Number of Elements1
Operating Temperature (Max)125 °C
Operating Temperature (Min)-55 °C
Output TypeComplementary
Package Length0.091 in
Package Name8-VFSOP, 8-VSSOP
Package Width2.3 mm
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply (Maximum)5.5 V
Voltage - Supply (Minimum)1.65 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

LVC Characterization Information
CMOS Power Consumption and CPD Calculation (Rev. B)
Design Summary for WCSP Little Logic (Rev. B)
LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)
Live Insertion
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
LOGIC Pocket Data Book (Rev. B)
Power-Up Behavior of Clocked Devices (Rev. B)
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
Use of the CMOS Unbuffered Inverter in Oscillator Circuits
TI IBIS File Creation, Validation, and Distribution Processes
Selecting the Right Level Translation Solution (Rev. A)
How to Select Little Logic (Rev. A)
Signal Switch Data Book (Rev. A)
Implications of Slow or Floating CMOS Inputs (Rev. E)
Understanding Advanced Bus-Interface Products Design Guide
Single Positive Edge Triggered D-Type Flip-Flop With Clear And Preset datasheet
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Input and Output Characteristics of Digital Integrated Circuits
Standard Linear & Logic for PCs, Servers & Motherboards
STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS
SN74LVC2G74MDCUTEP Reliability Report
Low-Voltage Logic (LVC) Designer's Guide
Logic Guide (Rev. AB)
Texas Instruments Little Logic Application Report
Little Logic Guide 2018 (Rev. G)
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices