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M38510/30109BEA - M38510/30103BEA

M38510/30109BEA

Active
Texas Instruments

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

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M38510/30109BEA - M38510/30103BEA

M38510/30109BEA

Active
Texas Instruments

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationM38510/30109BEASN54LS109A Series
--
Clock Frequency33 MHz33 MHz
Current - Output High, Low4 mA4 mA
Current - Output High, Low-400 µA
Current - Output High, Low-4 mA
Current - Quiescent (Iq)8 mA8 mA
FunctionReset, Set(Preset)Reset, Set(Preset)
Grade-Military
Max Propagation Delay @ V, Max CL40 ns40 ns
Mounting TypeThrough HoleThrough Hole
Number of Bits per Element11
Number of Elements [custom]22
Operating Temperature [Max]125 °C125 °C
Operating Temperature [Min]-55 C-55 C
Output TypeComplementaryComplementary
Package / Case16-CDIP (0.300", 7.62mm)16-CDIP (0.300", 7.62mm)
Qualification-MIL-PRF-38535L
Supplier Device Package16-CDIP16-CDIP
Trigger TypePositive EdgePositive Edge
TypeJK TypeJK Type
Voltage - Supply [Max]5.5 V5.5 V
Voltage - Supply [Min]4.5 V4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

SN54LS109A Series

Dual J-K Positive-Edge-Triggered Flip-Flops With Preset And Clear

PartVoltage - Supply [Max]Voltage - Supply [Min]Output TypeCurrent - Output High, LowCurrent - Quiescent (Iq)Package / CaseOperating Temperature [Min]Operating Temperature [Max]TypeMax Propagation Delay @ V, Max CLSupplier Device PackageNumber of Bits per ElementClock FrequencyMounting TypeFunctionTrigger TypeNumber of Elements [custom]Current - Output High, Low [custom]Current - Output High, Low [custom]GradeQualification
Texas Instruments
JM38510/30109BFA
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C. These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C.
Texas Instruments
M38510/30109BEA
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C. These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C.
5.5 V
4.5 V
Complementary
4 mA
8 mA
16-CDIP (0.300", 7.62mm)
-55 C
125 °C
JK Type
40 ns
16-CDIP
1
33 MHz
Through Hole
Reset, Set(Preset)
Positive Edge
2
Texas Instruments
JM38510/30109BEA
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C. These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C.
5.5 V
4.5 V
Complementary
4 mA
8 mA
16-CDIP (0.300", 7.62mm)
-55 C
125 °C
JK Type
40 ns
16-CDIP
1
33 MHz
Through Hole
Reset, Set(Preset)
Positive Edge
2
400 µA
4 mA
Military
MIL-PRF-38535L

Description

General part information

SN54LS109A Series

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.

The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C.

These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.