SN54LS109A Series
Dual J-K Positive-Edge-Triggered Flip-Flops With Preset And Clear
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Dual J-K Positive-Edge-Triggered Flip-Flops With Preset And Clear
| Part | Voltage - Supply [Max] | Voltage - Supply [Min] | Output Type | Current - Output High, Low | Current - Quiescent (Iq) | Package / Case | Operating Temperature [Min] | Operating Temperature [Max] | Type | Max Propagation Delay @ V, Max CL | Supplier Device Package | Number of Bits per Element | Clock Frequency | Mounting Type | Function | Trigger Type | Number of Elements [custom] | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Grade | Qualification |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments JM38510/30109BFA | |||||||||||||||||||||
Texas Instruments M38510/30109BEA | 5.5 V | 4.5 V | Complementary | 4 mA | 8 mA | 16-CDIP (0.300", 7.62mm) | -55 C | 125 °C | JK Type | 40 ns | 16-CDIP | 1 | 33 MHz | Through Hole | Reset, Set(Preset) | Positive Edge | 2 | ||||
Texas Instruments JM38510/30109BEA | 5.5 V | 4.5 V | Complementary | 4 mA | 8 mA | 16-CDIP (0.300", 7.62mm) | -55 C | 125 °C | JK Type | 40 ns | 16-CDIP | 1 | 33 MHz | Through Hole | Reset, Set(Preset) | Positive Edge | 2 | 400 µA | 4 mA | Military | MIL-PRF-38535L |
Key Features
• Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPsDependable Texas Instruments Quality and ReliabilityPackage Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPsDependable Texas Instruments Quality and Reliability
Description
AI
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C.
These devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The SN54109 and SN54LS109A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74109 and SN74LS109A are characterized for operation from 0°C to 70°C.