CDC2509CPW
Active1-TO-9 PLL CLOCK DRIVER FOR SDRAM APPLICATIONS
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CDC2509CPW
Active1-TO-9 PLL CLOCK DRIVER FOR SDRAM APPLICATIONS
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CDC2509CPW | CDC2509 Series |
|---|---|---|
| Differential - Input:Output [custom] | False | False |
| Differential - Input:Output [custom] | False | False |
| Divider/Multiplier [custom] | False | False |
| Divider/Multiplier [custom] | False | False |
| Frequency - Max [Max] | 125 MHz | 125 MHz |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 85 °C | 70 - 85 °C |
| Operating Temperature [Min] | 0 °C | 0 °C |
| Output | LVTTL | LVTTL |
| Package / Case | 24-TSSOP | 24-TSSOP |
| Package / Case [y] | 4.4 mm | 4.4 mm |
| Package / Case [y] | 0.173 " | 0.173 " |
| PLL | Yes with Bypass | Yes with Bypass |
| Ratio - Input:Output [custom] | 1 | 1 |
| Ratio - Input:Output [custom] | 9 | 9 |
| Supplier Device Package | 24-TSSOP | 24-TSSOP |
| Type | PLL Clock Driver | PLL Clock Driver |
| Voltage - Supply [Max] | 3.6 V | 3.6 V |
| Voltage - Supply [Min] | 3 V | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 120 | $ 8.60 | |
| Texas Instruments | TUBE | 1 | $ 10.24 | |
| 100 | $ 8.35 | |||
| 250 | $ 6.56 | |||
| 1000 | $ 5.57 | |||
CDC2509 Series
1-to-9 PLL clock driver for SDRAM applications
| Part | Mounting Type | Package / Case [y] | Package / Case [y] | Package / Case | Divider/Multiplier [custom] | Divider/Multiplier [custom] | Number of Circuits | Supplier Device Package | Output | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | PLL | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Voltage - Supply [Max] | Voltage - Supply [Min] | Frequency - Max [Max] | Operating Temperature [Min] | Operating Temperature [Max] | Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDC2509CPW | Surface Mount | 4.4 mm | 0.173 " | 24-TSSOP | 1 | 24-TSSOP | LVTTL | 1 | 9 | Yes with Bypass | 3.6 V | 3 V | 125 MHz | 0 °C | 85 °C | PLL Clock Driver | ||||
Texas Instruments CDC2509BPW | Surface Mount | 4.4 mm | 0.173 " | 24-TSSOP | 1 | 24-TSSOP | LVTTL | 1 | 9 | Yes with Bypass | 3.6 V | 3 V | 125 MHz | 0 °C | 70 ░C | PLL Clock Driver | ||||
Texas Instruments CDC2509PWR | Surface Mount | 4.4 mm | 0.173 " | 24-TSSOP | 1 | 24-TSSOP | LVTTL | 1 | 9 | Yes with Bypass | 3.6 V | 3 V | 125 MHz | 0 °C | 70 ░C | PLL Clock Driver | ||||
Texas Instruments CDC2509APWR | Surface Mount | 4.4 mm | 0.173 " | 24-TSSOP | 1 | 24-TSSOP | LVTTL | 1 | 9 | Yes with Bypass | 3.6 V | 3 V | 0 °C | 70 ░C | PLL Clock Driver | |||||
Texas Instruments CDC2509CPWR | Surface Mount | 4.4 mm | 0.173 " | 24-TSSOP | 1 | 24-TSSOP | LVTTL | 1 | 9 | Yes with Bypass | 3.6 V | 3 V | 125 MHz | 0 °C | 85 °C | PLL Clock Driver | ||||
Texas Instruments CDC2509BPWR | Surface Mount | 4.4 mm | 0.173 " | 24-TSSOP | 1 | 24-TSSOP | LVTTL | 1 | 9 | Yes with Bypass | 3.6 V | 3 V | 125 MHz | 0 °C | 70 ░C | PLL Clock Driver |
Description
General part information
CDC2509 Series
The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Documents
Technical documentation and resources