Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | SN74LS194ADR | 74LS194 Series |
|---|---|---|
| - | - | |
| Function | Universal | Universal |
| Logic Type | Register, Bidirectional | Register, Bidirectional |
| Mounting Type | Surface Mount | Surface Mount, Through Hole |
| Number of Bits per Element | 4 | 4 |
| Number of Elements [custom] | 1 | 1 |
| Operating Temperature [Max] | 70 ░C | 70 ░C |
| Operating Temperature [Min] | 0 °C | 0 °C |
| Output Type | Push-Pull | Push-Pull |
| Package / Case | 16-SOIC | 16-SOIC, 16-DIP |
| Package / Case | 3.9 mm Width, 0.154 in | 0.154 - 7.62 mm Width |
| Supplier Device Package | 16-SOIC | 16-SOIC, 16-PDIP |
| Voltage - Supply [Max] | 5.25 V | 5.25 V |
| Voltage - Supply [Min] | 4.75 V | 4.75 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
74LS194 Series
Bidirectional universal shift registers
| Part | Voltage - Supply [Min] | Voltage - Supply [Max] | Package / Case | Package / Case | Output Type | Supplier Device Package | Operating Temperature [Max] | Operating Temperature [Min] | Mounting Type | Number of Elements [custom] | Logic Type | Function | Number of Bits per Element |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SN74LS194ADThese bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.
Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high.
These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.
Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high. | 4.75 V | 5.25 V | 16-SOIC | 0.154 in, 3.9 mm Width | Push-Pull | 16-SOIC | 70 ░C | 0 °C | Surface Mount | 1 | Register, Bidirectional | Universal | 4 |
4.75 V | 5.25 V | 16-SOIC | 0.154 in, 3.9 mm Width | Push-Pull | 16-SOIC | 70 ░C | 0 °C | Surface Mount | 1 | Register, Bidirectional | Universal | 4 | |
4.75 V | 5.25 V | 16-SOIC | 0.154 in, 3.9 mm Width | Push-Pull | 16-SOIC | 70 ░C | 0 °C | Surface Mount | 1 | Register, Bidirectional | Universal | 4 | |
Texas Instruments SN74LS194ANThese bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.
Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high.
These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.
Clocking of the shift register is inhibited when both mode control inputs are low. The mode controls of the SN54194/SN74194 should be changed only while the clock input is high. | 4.75 V | 5.25 V | 16-DIP | 0.3 in, 7.62 mm | Push-Pull | 16-PDIP | 70 ░C | 0 °C | Through Hole | 1 | Register, Bidirectional | Universal | 4 |
Description
General part information
74LS194 Series
These bidirectional shift registers are designed to incorporate virtually all of the features a system designer may want in a shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely:
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input.