CD74HC73M96

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Texas Instruments

HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET

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DocumentsLive Insertion Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc +13

CD74HC73M96

Active

Texas Instruments

HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET

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DocumentsLive Insertion Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc +13

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics commom to parts in this series

Specification	CD74HC73M96	74HC73 Series

Clock Frequency	60 MHz	60 MHz
Current - Output High, Low	5.2 mA, 5.2 mA	5.2 mA
Current - Quiescent (Iq)	4 çA	4 çA
Function	Reset	Reset
Input Capacitance	10 pF	10 pF
Max Propagation Delay @ V, Max CL	28 ns	28 ns
Mounting Type	Surface Mount	Surface Mount, Through Hole
Number of Bits per Element	1	1
Number of Elements [custom]	2	2
Operating Temperature [Max]	125 °C	125 °C
Operating Temperature [Min]	-55 C	-55 C
Output Type	Complementary	Complementary
Package / Case	3.9 mm	3.9 - 7.62 mm
Package / Case	0.154 in	0.154 - 0.3 in
Package / Case	14-SOIC	14-SOIC, 14-DIP
Trigger Type	Negative Edge	Negative Edge
Type	JK Type	JK Type
Voltage - Supply [Max]	6 V	6 V
Voltage - Supply [Min]	2 V	2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.51
		10	$ 0.41
		25	$ 0.38
		100	$ 0.28
		250	$ 0.25
		500	$ 0.21
		1000	$ 0.16
	Digi-Reel®	1	$ 0.51
		10	$ 0.41
		25	$ 0.38
		100	$ 0.28
		250	$ 0.25
		500	$ 0.21
		1000	$ 0.16
	Tape & Reel (TR)	2500	$ 0.14
		5000	$ 0.14
		12500	$ 0.13
		25000	$ 0.12
		62500	$ 0.11
Texas Instruments	LARGE T&R	1	$ 0.25
		100	$ 0.17
		250	$ 0.13
		1000	$ 0.09

74HC73 Series

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset

Part	Input Capacitance	Mounting Type	Output Type	Current - Output High, Low	Clock Frequency	Type	Operating Temperature [Min]	Operating Temperature [Max]	Max Propagation Delay @ V, Max CL	Number of Bits per Element	Current - Quiescent (Iq)	Function	Number of Elements [custom]	Package / Case	Package / Case	Package / Case	Trigger Type	Voltage - Supply [Min]	Voltage - Supply [Max]
Texas Instruments CD74HC73M96 Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width)	10 pF	Surface Mount	Complementary	5.2 mA, 5.2 mA	60 MHz	JK Type	-55 C	125 °C	28 ns	1	4 çA	Reset	2	3.9 mm	0.154 in	14-SOIC	Negative Edge	2 V	6 V
Texas Instruments CD74HC73EG4 Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-DIP (0.300", 7.62mm)	10 pF	Through Hole	Complementary	5.2 mA, 5.2 mA	60 MHz	JK Type	-55 C	125 °C	28 ns	1	4 çA	Reset	2	7.62 mm	0.3 in	14-DIP	Negative Edge	2 V	6 V
Texas Instruments CD74HC73MT Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width)	10 pF	Surface Mount	Complementary	5.2 mA, 5.2 mA	60 MHz	JK Type	-55 C	125 °C	28 ns	1	4 çA	Reset	2	3.9 mm	0.154 in	14-SOIC	Negative Edge	2 V	6 V
Texas Instruments CD74HC73M Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width)	10 pF	Surface Mount	Complementary	5.2 mA, 5.2 mA	60 MHz	JK Type	-55 C	125 °C	28 ns	1	4 çA	Reset	2	3.9 mm	0.154 in	14-SOIC	Negative Edge	2 V	6 V
Texas Instruments CD74HC73E Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-DIP (0.300", 7.62mm)	10 pF	Through Hole	Complementary	5.2 mA, 5.2 mA	60 MHz	JK Type	-55 C	125 °C	28 ns	1	4 çA	Reset	2	7.62 mm	0.3 in	14-DIP	Negative Edge	2 V	6 V

Description

General part information

74HC73 Series

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset

Documents

Technical documentation and resources

CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger datasheet (Rev. G)

Data sheet

CD74HC73M96

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CD74HC73M96

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Technical Specifications

Pricing

74HC73 Series

Description

74HC73 Series

Documents

Live Insertion

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Logic Guide (Rev. AB)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Implications of Slow or Floating CMOS Inputs (Rev. E)

Input and Output Characteristics of Digital Integrated Circuits

CMOS Power Consumption and CPD Calculation (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Designing With Logic (Rev. C)

Power-Up Behavior of Clocked Devices (Rev. B)

LOGIC Pocket Data Book (Rev. B)

Signal Switch Data Book (Rev. A)

SN54/74HCT CMOS Logic Family Applications and Restrictions

CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger datasheet (Rev. G)