74HC73 Series
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
Manufacturer: Texas Instruments
Catalog(2 parts)
| Part | Clock Frequency▲▼ | Current - Quiescent (Iq)▲▼ | Mounting Type | Function | Trigger Type | Number of Elements▲▼ | Output Type | Max Propagation Delay @ V, Max CL▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Type | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Input Capacitance▲▼ | Number of Bits per Element▲▼ | Package / Case | Package / Case▲▼ | Package / Case▲▼ | Current - Output High, Low▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
60000000 Hz | 0.000003999999989900971 A | Through Hole | Reset | Negative Edge | 2 ul | Complementary | 2.8000000540373552e-8 s | -55 °C | 125 °C | JK Type | 2 V | 6 V | 9.999999960041972e-12 F | 1 ul | 14-DIP | 0.007619999814778566 m | 0.007619999814778566 m | 0.005200000014156103 A, 0.005200000014156103 A | |
Texas Instruments CD74HC73MFlip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width) | 60000000 Hz | 0.000003999999989900971 A | Surface Mount | Reset | Negative Edge | 2 ul | Complementary | 2.8000000540373552e-8 s | -55 °C | 125 °C | JK Type | 2 V | 6 V | 9.999999960041972e-12 F | 1 ul | 14-SOIC | 0.003899999894201755 m | 0.003911599982529879 m | 0.005200000014156103 A, 0.005200000014156103 A |
Key Features
• Hysteresis on clock inputs for improved noise immunity and increased input rise and fall timesAsynchronous resetComplementary outputsBuffered inputsTypical fMAX= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOHHysteresis on clock inputs for improved noise immunity and increased input rise and fall timesAsynchronous resetComplementary outputsBuffered inputsTypical fMAX= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOH