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CD74HC4059EG4 - N-24-DIP Pkg

CD74HC4059EG4

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Texas Instruments

IC DIVIDER BY N 16-BIT 24DIP

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CD74HC4059EG4 - N-24-DIP Pkg

CD74HC4059EG4

Active
Texas Instruments

IC DIVIDER BY N 16-BIT 24DIP

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Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationCD74HC4059EG474HC4059 Series
Count Rate32 MHz32 MHz
DirectionDownDown
Logic TypeDivide-by-NDivide-by-N
Mounting TypeThrough HoleSurface Mount, Through Hole
Number of Bits per Element [custom]1616
Number of Elements [custom]11
Operating Temperature [Max]125 °C125 °C
Operating Temperature [Min]-55 °C-55 °C
Package / Case15.24 mm15.24 mm
Package / Case24-DIP24-SOIC, 24-DIP
Package / Case0.6 in0.6 in
Package / Case-7.5 mm
Package / Case-0.295 in
ResetAsynchronousAsynchronous
Supplier Device Package24-PDIP24-SOIC, 24-PDIP
TimingSynchronousSynchronous
Trigger TypePositive EdgePositive Edge
Voltage - Supply [Max]6 V6 V
Voltage - Supply [Min]2 V2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

74HC4059 Series

High Speed CMOS Logic CMOS Programmable Divide-by-N Counter

PartLogic TypeNumber of Bits per Element [custom]Supplier Device PackageVoltage - Supply [Max]Voltage - Supply [Min]Package / Case [y]Package / Case [x]Package / CaseTrigger TypeTimingDirectionMounting TypeCount RateResetNumber of Elements [custom]Operating Temperature [Min]Operating Temperature [Max]Package / CasePackage / Case
Texas Instruments
CD74HC4059M96
The ’HC4059 are high-speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series. These devices are divide-by-N down-counters that can be programmed to divide an input frequency by any number "N" from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The down-counter is preset by means of 16 jam inputs. The three Mode-Select Inputs Ka,Kband Kcdetermine the modulus ("divide-by" number) of the first and last counting sections in accordance with the truth table. Every time the first (fastest) counting section goes through one cycle, it reduces by 1 the number that has been preset (jammed) into the three decades of the intermediate counting section an the last counting section, which consists of flip-flops that are not needed for opening the first counting section. For example, in the10) counters presettable by means of Jam Inputs J5 through J16. The Mode-Select Inputs permit frequency-synthesizer channel separations of 10, 12.5, 20, 25 or 50 parts. These inputs set the maximum value of N at 9999 (when the first counting section divides by 5 or 10) or 15,999 (when the first counting section divides by 8, 4, or 2). The three decades of the intermediate counter can be preset to a binary 15 instead of a binary 9, while their place values are still 1, 10, and 100, multiplied by the number of the8 mode, the number from which counting down begins can be preset to:3rd Decade 15002nd Decade 1501st Decade 15Last Counting Section 1000 The total of these numbers (2665) times 8 equals 12,320. The first counting section can be preset to 7. Therefore, 21,327 is the maximum possible count in the8 mode. The highest count of the various modes is shown in the Extended Counter Range column. Control inputs Kband Kccan be used to initiate and lock the counter in the "master preset" state. In this condition the flip-flops in the counter are preset in accordance with the jam inputs and the counter remains in that state as long as Kband Kcboth remain low. The counter begins to count down from the preset state when a counting mode other than the master preset mode is selected. The counter should always be put in the master preset mode before the5 mode is selected. Whenever the master preset mode is used, control signals Kb= "low" and Kc= "low" must be applied for at least 3 full clock pulses. After Preset Mode inputs have been changed to one of the8 mode). If the Master Preset mode is started two clock cycles or less before an output pulse, the output pulse will appear at the time due. If the Master Preset Mode is not used, the counter jumps back to the "Jam" count when the output pulse appears. A "high" on the Latch Enable input will cause the counter output to remain high once an output pulse occurs, and to remain in the high state until the latch input returns to "low". If the Latch Enable is "low", the output pulse will remain high for only one cycle of the clock-input signal. The ’HC4059 are high-speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series. These devices are divide-by-N down-counters that can be programmed to divide an input frequency by any number "N" from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The down-counter is preset by means of 16 jam inputs. The three Mode-Select Inputs Ka,Kband Kcdetermine the modulus ("divide-by" number) of the first and last counting sections in accordance with the truth table. Every time the first (fastest) counting section goes through one cycle, it reduces by 1 the number that has been preset (jammed) into the three decades of the intermediate counting section an the last counting section, which consists of flip-flops that are not needed for opening the first counting section. For example, in the10) counters presettable by means of Jam Inputs J5 through J16. The Mode-Select Inputs permit frequency-synthesizer channel separations of 10, 12.5, 20, 25 or 50 parts. These inputs set the maximum value of N at 9999 (when the first counting section divides by 5 or 10) or 15,999 (when the first counting section divides by 8, 4, or 2). The three decades of the intermediate counter can be preset to a binary 15 instead of a binary 9, while their place values are still 1, 10, and 100, multiplied by the number of the8 mode, the number from which counting down begins can be preset to:3rd Decade 15002nd Decade 1501st Decade 15Last Counting Section 1000 The total of these numbers (2665) times 8 equals 12,320. The first counting section can be preset to 7. Therefore, 21,327 is the maximum possible count in the8 mode. The highest count of the various modes is shown in the Extended Counter Range column. Control inputs Kband Kccan be used to initiate and lock the counter in the "master preset" state. In this condition the flip-flops in the counter are preset in accordance with the jam inputs and the counter remains in that state as long as Kband Kcboth remain low. The counter begins to count down from the preset state when a counting mode other than the master preset mode is selected. The counter should always be put in the master preset mode before the5 mode is selected. Whenever the master preset mode is used, control signals Kb= "low" and Kc= "low" must be applied for at least 3 full clock pulses. After Preset Mode inputs have been changed to one of the8 mode). If the Master Preset mode is started two clock cycles or less before an output pulse, the output pulse will appear at the time due. If the Master Preset Mode is not used, the counter jumps back to the "Jam" count when the output pulse appears. A "high" on the Latch Enable input will cause the counter output to remain high once an output pulse occurs, and to remain in the high state until the latch input returns to "low". If the Latch Enable is "low", the output pulse will remain high for only one cycle of the clock-input signal.
Divide-by-N
16
24-SOIC
6 V
2 V
7.5 mm
0.295 in
24-SOIC
Positive Edge
Synchronous
Down
Surface Mount
32 MHz
Asynchronous
1
-55 °C
125 °C
Texas Instruments
CD74HC4059EG4
Counter IC Divide-by-N 1 Element 16 Bit Positive Edge 24-PDIP
Divide-by-N
16
24-PDIP
6 V
2 V
24-DIP
Positive Edge
Synchronous
Down
Through Hole
32 MHz
Asynchronous
1
-55 °C
125 °C
15.24 mm
0.6 in
Texas Instruments
CD74HC4059E
Counter IC Divide-by-N 1 Element 16 Bit Positive Edge 24-PDIP
Divide-by-N
16
24-PDIP
6 V
2 V
24-DIP
Positive Edge
Synchronous
Down
Through Hole
32 MHz
Asynchronous
1
-55 °C
125 °C
15.24 mm
0.6 in

Description

General part information

74HC4059 Series

The ’HC4059 are high-speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series. These devices are divide-by-N down-counters that can be programmed to divide an input frequency by any number "N" from 3 to 15,999. The output signal is a pulse one clock cycle wide occurring at a rate equal to the input frequency divide by N. The down-counter is preset by means of 16 jam inputs.

The three Mode-Select Inputs Ka,Kband Kcdetermine the modulus ("divide-by" number) of the first and last counting sections in accordance with the truth table. Every time the first (fastest) counting section goes through one cycle, it reduces by 1 the number that has been preset (jammed) into the three decades of the intermediate counting section an the last counting section, which consists of flip-flops that are not needed for opening the first counting section. For example, in the10) counters presettable by means of Jam Inputs J5 through J16.

The Mode-Select Inputs permit frequency-synthesizer channel separations of 10, 12.5, 20, 25 or 50 parts. These inputs set the maximum value of N at 9999 (when the first counting section divides by 5 or 10) or 15,999 (when the first counting section divides by 8, 4, or 2).

Documents

Technical documentation and resources