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84074012A - 5962-7802301Q2A

84074012A

Active
Texas Instruments

MILITARY 8-CH, 2-V TO 6-V INVERTERS WITH 3-STATE OUTPUTS

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DocumentsLOGIC Pocket Data Book (Rev. B)Implications of Slow or Floating CMOS Inputs (Rev. E)+12
84074012A - 5962-7802301Q2A

84074012A

Active
Texas Instruments

MILITARY 8-CH, 2-V TO 6-V INVERTERS WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsLOGIC Pocket Data Book (Rev. B)Implications of Slow or Floating CMOS Inputs (Rev. E)+12
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Specification84074012A
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84074012 Series

Military 8-ch, 2-V to 6-V inverters with 3-state outputs

Part
Texas Instruments
84074012A
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

Description

General part information

84074012 Series

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HC240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.