N
Nexperia
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Buffers | 2 | 1 | The 74AUP2G34 is a dual buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCCrange from 0.8 V to 3.6 V. This device is fully specified for partial power... Read More | |
Nexperia74AUP2G3404 | Logic | 1 | 1 | |
| Buffers | 2 | 1 | The 74AUP2G34 is a dual buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCCrange from 0.8 V to 3.6 V. This device is fully specified for partial power... Read More | |
Nexperia74AUP2G58 | Logic | 1 | 1 | |
| Integrated Circuits (ICs) | 4 | 1 | The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. | |
| Integrated Circuits (ICs) | 4 | 1 | The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (nD) is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse (nCP). The nD input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. | |
Nexperia74AUP2G98 | Logic | 1 | 8 | |
| Gates and Inverters | 2 | 1 | The 74AUP3G0434 is a dual inverter and single buffer. | |
| Gates and Inverters | 2 | 1 | The 74AUP3G0434 is a dual inverter and single buffer. | |
| Buffers, Drivers, Receivers, Transceivers | 2 | 1 | The 74AUP3G34 is a triple buffer. | |