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74LVTH240 Series

8-ch, 2.7-V to 3.6-V inverters with bus-hold, TTL-compatible CMOS inputs and 3-state outputs

Manufacturer: Texas Instruments

Catalog(10 parts)

PartLogic TypeVoltage - Supply▲▼Voltage - Supply▲▼Operating Temperature▲▼Operating Temperature▲▼Mounting TypeNumber of Bits per Element▲▼Output TypeSupplier Device PackageNumber of Elements▲▼Package / Case▲▼Package / CaseCurrent - Output High, Low▲▼Package / Case▲▼
Texas Instruments
SN74LVTH240DW
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-SOIC
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-SOIC
2 ul
0.007493000011891127 m, 0.007499999832361937 m
20-SOIC
0.03200000151991844 A, 0.06400000303983688 A
Texas Instruments
SN74LVTH240DWRE4
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-SOIC
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-SOIC
2 ul
0.007493000011891127 m, 0.007499999832361937 m
20-SOIC
0.03200000151991844 A, 0.06400000303983688 A
Texas Instruments
SN74LVTH240NS
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-SO
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-SO
2 ul
0.0052999998442828655 m, 0.005308600142598152 m
20-SOIC
0.03200000151991844 A, 0.06400000303983688 A
Texas Instruments
SN74LVTH240IPWREP
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-TSSOP
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-TSSOP
2 ul
0.004394200164824724 m
20-TSSOP
0.03200000151991844 A, 0.06400000303983688 A
0.004399999976158142 m
Texas Instruments
SN74LVTH240NSR
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-SO
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-SO
2 ul
0.0052999998442828655 m, 0.005308600142598152 m
20-SOIC
0.03200000151991844 A, 0.06400000303983688 A
Texas Instruments
SN74LVTH240DWR
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-SOIC
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-SOIC
2 ul
0.007493000011891127 m, 0.007499999832361937 m
20-SOIC
0.03200000151991844 A, 0.06400000303983688 A
Texas Instruments
SN74LVTH240PWR
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-TSSOP
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-TSSOP
2 ul
0.004394200164824724 m
20-TSSOP
0.03200000151991844 A, 0.06400000303983688 A
0.004399999976158142 m
Texas Instruments
SN74LVTH240RGYR
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-VQFN (3.5x4.5)
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-VQFN (3.5x4.5)
2 ul
20-VFQFN Exposed Pad
0.03200000151991844 A, 0.06400000303983688 A
Texas Instruments
SN74LVTH240PW
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-TSSOP
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-TSSOP
2 ul
0.004394200164824724 m
20-TSSOP
0.03200000151991844 A, 0.06400000303983688 A
0.004399999976158142 m
Texas Instruments
SN74LVTH240GQNR
Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-BGA MICROSTAR JUNIOR (4x3)
Buffer, Inverting
2.700000047683716 V
3.5999999046325684 V
85 °C
-40 °C
Surface Mount
4 ul
3-State
20-BGA MICROSTAR JUNIOR (4x3)
2 ul
20-VFBGA
0.03200000151991844 A, 0.06400000303983688 A

Key Features

• Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)Support Unregulated Battery Operation Down to 2.7 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CIoffand Power-Up 3-State Support Hot InsertionBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 500 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)Support Unregulated Battery Operation Down to 2.7 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CIoffand Power-Up 3-State Support Hot InsertionBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 500 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)

Description

AI
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the devices pass data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the devices pass data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.