LMK05318B Series

Ultra-low jitter single channel network synchronizer clock with BAW

Catalog

Ultra-low jitter single channel network synchronizer clock with BAW

Part	Output	Differential Input	Differential Output	Type	Frequency - Max	Frequency - Max	Output Ratio	Input Ratio	Package Length	Package Name	Package Width	Voltage - Supply (Minimum)	Voltage - Supply (Maximum)	Number of Circuits	Operating Temperature (Min)	Operating Temperature (Max)	Input	PLL	Divider	Multiplier	Package / Case	Mounting Type
Texas Instruments LMK05318BRGZR	CML HCSL LVCMOS LVDS LVPECL	Yes	Yes	Clock Synchronizer and Jitter Cleaner	1.25GHz 200MHz 400MHz	1.25 GHz 200 MHz 400 MHz	8	3	7 mm	48-VQFN	7 mm	3.135 V	3.465 V	1	-40 °C	85 °C	LVCMOS	Yes with Bypass	Yes	Yes	48-VFQFN Exposed Pad	Surface Mount
Texas Instruments LMK05318BRGZT	HCSL LVCMOS LVDS LVPECL	Yes	Yes	Frequency Synthesizer		800 MHz	6	2	7 mm	48-VQFN	7 mm	3.135 V	3.465 V	1	-40 °C	85 °C	LVCMOS	Yes	Yes	No	48-VFQFN Exposed Pad	Surface Mount

Catalog

Ultra-low jitter single channel network synchronizer clock with BAW

Description

The LMK05318B is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links. The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs. The LMK05318B is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links. The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.