8101701 Series
CMOS 4-Stage Parallel In/Parallel Out Shift Register
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
CMOS 4-Stage Parallel In/Parallel Out Shift Register
| Part | Voltage - Supply [Max] | Voltage - Supply [Min] | Mounting Type | Output Type | Number of Elements [custom] | Function | Package / Case | Logic Type | Number of Bits per Element | Supplier Device Package | Operating Temperature [Min] | Operating Temperature [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments 8101701EA | 18 V | 3 V | Through Hole | Complementary | 1 | Parallel or Serial to Serial | 16-CDIP (0.300", 7.62mm) | Shift Register | 4 | 16-CDIP | -55 C | 125 °C |
Key Features
• 4-Stage clocked shift operationSynchronous parallel entry on all 4 stagesJK\ inputs on first stageAsynchronous True/Complement control on all outputsStatic flip-flop operation; Master-slave configurationBuffered inputs and outputsHigh speed — 12 MHz (typ.) at VDD= 10 V100% tested for quiescent current at 20 VStandardized, symmetrical output characteristics5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"Applications:Counters, RegistersArithmetic-unit registersShift-left — shift right registersSerial-to-parallel/parallel-to-serial conversionsSequence generationControl circuitsCode conversion4-Stage clocked shift operationSynchronous parallel entry on all 4 stagesJK\ inputs on first stageAsynchronous True/Complement control on all outputsStatic flip-flop operation; Master-slave configurationBuffered inputs and outputsHigh speed — 12 MHz (typ.) at VDD= 10 V100% tested for quiescent current at 20 VStandardized, symmetrical output characteristics5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13A, "Standard Specifications for Description of 'B' Series CMOS Devices"Applications:Counters, RegistersArithmetic-unit registersShift-left — shift right registersSerial-to-parallel/parallel-to-serial conversionsSequence generationControl circuitsCode conversion
Description
AI
CD4035B is a four-stage clocked signal serial register with provision for synchronous PARALLEL inputs to each stage and SERIAL inputs to the first stage via JK\ logic. Register stages 2, 3, and 4 are coupled in a serial D flip-flop configuration when the register is in the serial mode (PARALLEL/SERIAL control low).
Parallel entry into each register stage is permitted when the PARALLEL/SERIAL control is high.
In the parallel or serial mode information is transferred on positive clock transitions.
When the TRUE/COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. THe TRUE/COMPLEMENT control functions asynchronously with respect to the CLOCK signal.
JK\ input logic is provided on the first stage SERIAL input to minimize logic requirements particularly in counting and sequence-generation applications. With JK\ inputs connected together, the first stage becomes a D flip-flop. An asynchronous common RESET is also provided.
The CD4035B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4035B is a four-stage clocked signal serial register with provision for synchronous PARALLEL inputs to each stage and SERIAL inputs to the first stage via JK\ logic. Register stages 2, 3, and 4 are coupled in a serial D flip-flop configuration when the register is in the serial mode (PARALLEL/SERIAL control low).
Parallel entry into each register stage is permitted when the PARALLEL/SERIAL control is high.
In the parallel or serial mode information is transferred on positive clock transitions.
When the TRUE/COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. THe TRUE/COMPLEMENT control functions asynchronously with respect to the CLOCK signal.
JK\ input logic is provided on the first stage SERIAL input to minimize logic requirements particularly in counting and sequence-generation applications. With JK\ inputs connected together, the first stage becomes a D flip-flop. An asynchronous common RESET is also provided.
The CD4035B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).