TMS320VC5409A Series

Fixed-Point DSP

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Catalog

Fixed-Point DSP

Part	Interface	Voltage - Core	Clock Rate	Supplier Device Package	Non-Volatile Memory	Non-Volatile Memory	On-Chip RAM	Package / Case	Voltage - I/O	Mounting Type	Operating Temperature [Min]	Operating Temperature [Max]	Type
Texas Instruments TMS320VC5409APGE16	Host Interface, McBSP	1.6 V	160 MHz	144-LQFP (20x20)	ROM	32 kB	64 kB	144-LQFP	3.3 V	Surface Mount	-40 °C	100 °C	Fixed Point
Texas Instruments TMS320VC5409AZWS16	Host Interface, McBSP	1.6 V	160 MHz	144-NFBGA (12x12)	ROM	32 kB	64 kB	144-LFBGA	3.3 V	Surface Mount	-40 °C	100 °C	Fixed Point
Texas Instruments TMS320VC5409AGWS12	Host Interface, McBSP	1.5 V	120 MHz	144-NFBGA (12x12)	ROM	32 kB	64 kB	144-LFBGA	3.3 V	Surface Mount	-40 °C	100 °C	Fixed Point
Texas Instruments TMS320VC5409AGWS16	Host Interface, McBSP	1.6 V	160 MHz	144-NFBGA (12x12)	ROM	32 kB	64 kB	144-LFBGA	3.3 V	Surface Mount	-40 °C	100 °C	Fixed Point
Texas Instruments TMS320VC5409APGE12	Host Interface, McBSP	1.5 V	120 MHz	144-LQFP (20x20)	ROM	32 kB	64 kB	144-LQFP	3.3 V	Surface Mount	-40 °C	100 °C	Fixed Point
Texas Instruments TMS320VC5409AZWS12	Host Interface, McBSP	1.5 V	120 MHz	144-NFBGA (12x12)	ROM	32 kB	64 kB	144-LFBGA	3.3 V	Surface Mount	-40 °C	100 °C	Fixed Point

Key Features

• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators17- \xD7 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) OperationCompare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi OperatorExponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single CycleTwo Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)Data Bus With a Bus Holder FeatureExtended Addressing Mode for 8M \xD7 16-Bit Maximum Addressable External Program Space32K x 16-Bit On-Chip RAM Composed of:Four Blocks of 8K \xD7 16-Bit On-Chip Dual-Access Program/Data RAM16K \xD7 16-Bit On-Chip ROM Configured for Program MemoryEnhanced External Parallel Interface (XIO2)Single-Instruction-Repeat and Block-Repeat Operations for Program CodeBlock-Memory-Move Instructions for Better Program and Data ManagementInstructions With a 32-Bit Long Word OperandInstructions With Two- or Three-Operand ReadsArithmetic Instructions With Parallel Store and Parallel LoadConditional Store InstructionsFast Return From InterruptOn-Chip PeripheralsSoftware-Programmable Wait-State Generator and Programmable Bank-SwitchingOn-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source(1)One 16-Bit TimerSix-Channel Direct Memory Access (DMA) ControllerThree Multichannel Buffered Serial Ports (McBSPs)8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down ModesCLKOUT Off Control to Disable CLKOUTOn-Chip Scan-Based Emulation Logic, IEEE Std 1149.1(2)(JTAG) Boundary Scan Logic144-Pin Ball Grid Array (BGA) (GGU Suffix)144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS)8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)3.3-V I/O Supply Voltage (160 and 120 MIPS)1.6-V Core Supply Voltage (160 MIPS)1.5-V Core Supply Voltage (120 MIPS)(1)The on-chip oscillator is not available on all 5409A devices. For applicable devices, see theTMS320VC5409A Digital Signal Processor Silicon Errata(literature number SPRZ186).(2)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.NOTE: This data manual is designed to be used in conjunction with theTMS320C54x\x99 DSP Functional Overview(literature number SPRU307).TMS320C54x, MicroStar BGA, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments.All trademarks are the property of their respective owners.Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators17- \xD7 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) OperationCompare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi OperatorExponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single CycleTwo Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)Data Bus With a Bus Holder FeatureExtended Addressing Mode for 8M \xD7 16-Bit Maximum Addressable External Program Space32K x 16-Bit On-Chip RAM Composed of:Four Blocks of 8K \xD7 16-Bit On-Chip Dual-Access Program/Data RAM16K \xD7 16-Bit On-Chip ROM Configured for Program MemoryEnhanced External Parallel Interface (XIO2)Single-Instruction-Repeat and Block-Repeat Operations for Program CodeBlock-Memory-Move Instructions for Better Program and Data ManagementInstructions With a 32-Bit Long Word OperandInstructions With Two- or Three-Operand ReadsArithmetic Instructions With Parallel Store and Parallel LoadConditional Store InstructionsFast Return From InterruptOn-Chip PeripheralsSoftware-Programmable Wait-State Generator and Programmable Bank-SwitchingOn-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source(1)One 16-Bit TimerSix-Channel Direct Memory Access (DMA) ControllerThree Multichannel Buffered Serial Ports (McBSPs)8/16-Bit Enhanced Parallel Host-Port Interface (HPI8/16)Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down ModesCLKOUT Off Control to Disable CLKOUTOn-Chip Scan-Based Emulation Logic, IEEE Std 1149.1(2)(JTAG) Boundary Scan Logic144-Pin Ball Grid Array (BGA) (GGU Suffix)144-Pin Low-Profile Quad Flatpack (LQFP) (PGE Suffix)6.25-ns Single-Cycle Fixed-Point Instruction Execution Time (160 MIPS)8.33-ns Single-Cycle Fixed-Point Instruction Execution Time (120 MIPS)3.3-V I/O Supply Voltage (160 and 120 MIPS)1.6-V Core Supply Voltage (160 MIPS)1.5-V Core Supply Voltage (120 MIPS)(1)The on-chip oscillator is not available on all 5409A devices. For applicable devices, see theTMS320VC5409A Digital Signal Processor Silicon Errata(literature number SPRZ186).(2)IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.NOTE: This data manual is designed to be used in conjunction with theTMS320C54x\x99 DSP Functional Overview(literature number SPRU307).TMS320C54x, MicroStar BGA, C54x, TMS320C5000, C5000, TMS320 are trademarks of Texas Instruments.All trademarks are the property of their respective owners.

Description

The TMS320VC5409A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5409A unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5409A also includes the control mechanisms to manage interrupts, The TMS320VC5409A fixed-point, digital signal processor (DSP) (hereafter referred to as the 5409A unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The 5409A also includes the control mechanisms to manage interrupts,