CLVC1G374 Series
Automotive Catalog Single D-Type Flip-Flop with 3-State Output
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Automotive Catalog Single D-Type Flip-Flop with 3-State Output
| Part | Function | Current - Quiescent (Iq) | Mounting Type | Trigger Type | Current - Output High, Low | Operating Temperature [Min] | Operating Temperature [Max] | Qualification | Package / Case | Number of Bits per Element | Max Propagation Delay @ V, Max CL | Voltage - Supply [Max] | Voltage - Supply [Min] | Output Type | Number of Elements [custom] | Supplier Device Package | Grade | Type | Input Capacitance |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CLVC1G374QDCKRQ1 | Standard | 10 µA | Surface Mount | Positive Edge | 40 mA, 40 mA | -40 °C | 125 °C | AEC-Q100 | 6-TSSOP, SC-88, SOT-363 | 1 | 5 ns | 5.5 V | 1.65 V | Tri-State, Non-Inverted | 1 | SC-70-6 | Automotive | D-Type | 3 pF |
Texas Instruments CLVC1G374QDBVRQ1 | Standard | 10 µA | Surface Mount | Positive Edge | 40 mA, 40 mA | -40 °C | 125 °C | AEC-Q100 | SOT-23-6 | 1 | 5 ns | 5.5 V | 1.65 V | Tri-State, Non-Inverted | 1 | SOT-23-6 | Automotive | D-Type | 3 pF |
Key Features
• Qualified for Automotive ApplicationsSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Partial-Power-Down ModeOperationLatch-Up Performance Exceeds 100 mA Per JESD 78,Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Qualified for Automotive ApplicationsSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VIoffSupports Partial-Power-Down ModeOperationLatch-Up Performance Exceeds 100 mA Per JESD 78,Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)
Description
AI
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input.
A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input.
A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.