74SSTV16859 Series

200-MHz, 13-bit to 26-bit registered buffer with SSTL_2 inputs and outputs

Catalog(4 parts)

Part	Package / Case	Supply Voltage▲▼	Supply Voltage▲▼	Supplier Device Package	Supplier Device Package▲▼	Supplier Device Package▲▼	Number of Bits▲▼	Operating Temperature▲▼	Mounting Type	Logic Type	Package / Case▲▼	Package / Case▲▼
Texas Instruments SN74SSTV16859RGQ8 Registered Buffer with SSTL_2 Compatible I/O for DDR IC 56-VQFN (8x8)	56-VFQFN Exposed Pad	2.700000047683716 V	2.299999952316284 V	56-VQFN	8 ul	8 ul	13 ul, 26 ul	70 °C	Surface Mount	Registered Buffer with SSTL_2 Compatible I/O for DDR
Texas Instruments SN74SSTV16859DGG Registered Buffer with SSTL_2 Compatible I/O for DDR IC 64-TSSOP	64-TFSOP	2.700000047683716 V	2.299999952316284 V	64-TSSOP			13 ul, 26 ul	70 °C	Surface Mount	Registered Buffer with SSTL_2 Compatible I/O for DDR	0.006095999851822853 m	0.006099999882280827 m
Texas Instruments 74SSTV16859DGGRG4 Registered Buffer with SSTL_2 Compatible I/O for DDR IC 64-TSSOP	64-TFSOP	2.700000047683716 V	2.299999952316284 V	64-TSSOP			13 ul, 26 ul	70 °C	Surface Mount	Registered Buffer with SSTL_2 Compatible I/O for DDR	0.006095999851822853 m	0.006099999882280827 m
Texas Instruments SN74SSTV16859RGQR Registered Buffer with SSTL_2 Compatible I/O for DDR IC 56-VQFN (8x8)	56-VFQFN Exposed Pad	2.700000047683716 V	2.299999952316284 V	56-VQFN	8 ul	8 ul	13 ul, 26 ul	70 °C	Surface Mount	Registered Buffer with SSTL_2 Compatible I/O for DDR

Key Features

• Member of the Texas Instruments Widebus™ Family1-to-2 Outputs to Support Stacked DDR DIMMsSupports SSTL_2 Data InputsOutputs Meet SSTL_2 Class II SpecificationsDifferential Clock (CLK and CLK\) InputsSupports LVCMOS Switching Levels on the RESET\ InputRESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs LowPinout Optimizes DIMM PCB LayoutLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus is a trademark of Texas Instruments.Member of the Texas Instruments Widebus™ Family1-to-2 Outputs to Support Stacked DDR DIMMsSupports SSTL_2 Data InputsOutputs Meet SSTL_2 Class II SpecificationsDifferential Clock (CLK and CLK\) InputsSupports LVCMOS Switching Levels on the RESET\ InputRESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs LowPinout Optimizes DIMM PCB LayoutLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Widebus is a trademark of Texas Instruments.

Description

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCCoperation. All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are SSTL_2, Class II compatible. The SN74SSTV16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low. The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up. This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCCoperation. All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are SSTL_2, Class II compatible. The SN74SSTV16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low. The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.