CD54HC297 Series
High Speed CMOS Logic Digital Phase-Locked-Loop
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
High Speed CMOS Logic Digital Phase-Locked-Loop
| Part | Supply Voltage [Min] | Supply Voltage [Max] | Package / Case | Logic Type | Mounting Type | Operating Temperature [Min] | Operating Temperature [Max] | Supplier Device Package | Number of Bits |
|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD54HC297F3A | 2 V | 6 V | 16-CDIP (0.300", 7.62mm) | Digital Phase-Locked-Loop Filters | Through Hole | -55 °C | 125 °C | 16-CDIP | 4 |
Key Features
• Digital Design Avoids Analog Compensation ErrorsEasily Cascadable for Higher Order LoopsUseful Frequency RangeK-Clock...DC to 55MHz (Typ)I/D-Clock...DC to 35MHz (Typ)Dynamically Variable BandwidthVery Narrow Bandwidth AttainablePower-On ResetOutput CapabilityStandard...XORPDOUT, ECPDOUTBus Driver...I/DOUTFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICs’HC297 TypesOperation Voltage...2 to 6VHigh Noise Immunity NIL= 30%, NIH= 30% of VCCat 5VCD74HCT297 TypesOperation Voltage...4.5 to 5.5VDirect LSTTL Input Logic Compatibility VIL=0.8V (Max), VIH=2V (Min)CMOS Input Compatibility II1µA at VOL, VOHData sheet acquired from Harris SemiconductorDigital Design Avoids Analog Compensation ErrorsEasily Cascadable for Higher Order LoopsUseful Frequency RangeK-Clock...DC to 55MHz (Typ)I/D-Clock...DC to 35MHz (Typ)Dynamically Variable BandwidthVery Narrow Bandwidth AttainablePower-On ResetOutput CapabilityStandard...XORPDOUT, ECPDOUTBus Driver...I/DOUTFanout (Over Temperature Range)Standard Outputs...10 LSTTL LoadsBus Driver Outputs...15 LSTTL LoadsBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICs’HC297 TypesOperation Voltage...2 to 6VHigh Noise Immunity NIL= 30%, NIH= 30% of VCCat 5VCD74HCT297 TypesOperation Voltage...4.5 to 5.5VDirect LSTTL Input Logic Compatibility VIL=0.8V (Max), VIH=2V (Min)CMOS Input Compatibility II1µA at VOL, VOHData sheet acquired from Harris Semiconductor
Description
AI
The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).
These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops.
Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range.
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops.
The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop.
The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCCand temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.
The ’HC297 and CD74HCT297 are high-speed silicon gate CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL).
These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the exception of the divide-by-N counter, to build first-order phase-locked-loops.
Both EXCLUSIVE-OR (XORPD) and edge-controlled phase detectors (ECPD) are provided for maximum flexibility. The input signals for the EXCLUSIVE-OR phase detector must have a 50% duty factor to obtain the maximum lock-range.
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation (see Figure 2) or to cascade to higher order phase-locked-loops.
The length of the up/down K-counter is digitally programmable according to the K-counter function table. With A, B, C and D all LOW, the K-counter is disabled. With A HIGH and B, C and D LOW, the K-counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C and D are all programmed HIGH, the K-counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A to D inputs can maximize the overall performance of the digital phase-locked-loop.
The ’HC297 and CD74HCT297 can perform the classic first order phase-locked-loop function without using analog components. The accuracy of the digital phase-locked-loop (DPLL) is not affected by VCCand temperature variations but depends solely on accuracies of the K-clock and loop propagation delays.