LP2996A Series

The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, DDR3 and DDR3L VTT bus termination with VDDQmin of 1.35V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996A also incorporates a VSENSEpin to provide superior load regulation and a VREFoutput as a reference for the chipset and DIMMs. An additional feature found on the LP2996A is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. WhenSDis pulled low the VTToutput will tri-state providing a high impedance output, but, VREFwill remain active. A power savings advantage can be obtained in this mode through lower quiescent current. The LP2996A linear regulator is designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, DDR3 and DDR3L VTT bus termination with VDDQmin of 1.35V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. The LP2996A also incorporates a VSENSEpin to provide superior load regulation and a VREFoutput as a reference for the chipset and DIMMs. An additional feature found on the LP2996A is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. WhenSDis pulled low the VTToutput will tri-state providing a high impedance output, but, VREFwill remain active. A power savings advantage can be obtained in this mode through lower quiescent current.