74ABT16821 Series

20-Bit Bus Interface Flip-Flops With 3-State Outputs

Catalog(3 parts)

Part	Output Type	Supplier Device Package	Clock Frequency▲▼	Package / Case▲▼	Package / Case▲▼	Package / Case	Mounting Type	Number of Bits per Element▲▼	Type	Operating Temperature▲▼	Operating Temperature▲▼	Current - Quiescent (Iq)▲▼	Input Capacitance▲▼	Number of Elements▲▼	Current - Output High, Low▲▼	Function	Max Propagation Delay @ V, Max CL▲▼	Voltage - Supply▲▼	Voltage - Supply▲▼	Trigger Type
Texas Instruments SN74ABT16821DLR Flip Flop 2 Element D-Type 10 Bit Positive Edge 56-BSSOP (0.295", 7.50mm Width)	Tri-State, Non-Inverted	56-SSOP	150000000 Hz	0.007493000011891127 m	0.007499999832361937 m	56-BSSOP	Surface Mount	10 ul	D-Type	85 °C	-40 °C	0.0005000000237487257 A	3.4999999860146898e-12 F	2 ul	0.03200000151991844 A, 0.06400000303983688 A	Standard	5.099999977886682e-9 s	5.5 V	4.5 V	Positive Edge
Texas Instruments SN74ABT16821DLRG4 Flip Flop 2 Element D-Type 10 Bit Positive Edge 56-BSSOP (0.295", 7.50mm Width)	Tri-State, Non-Inverted	56-SSOP	150000000 Hz	0.007493000011891127 m	0.007499999832361937 m	56-BSSOP	Surface Mount	10 ul	D-Type	85 °C	-40 °C	0.0005000000237487257 A	3.4999999860146898e-12 F	2 ul	0.03200000151991844 A, 0.06400000303983688 A	Standard	5.099999977886682e-9 s	5.5 V	4.5 V	Positive Edge
Texas Instruments SN74ABT16821DL Flip Flop 2 Element D-Type 10 Bit Positive Edge 56-BSSOP (0.295", 7.50mm Width)	Tri-State, Non-Inverted	56-SSOP	150000000 Hz	0.007493000011891127 m	0.007499999832361937 m	56-BSSOP	Surface Mount	10 ul	D-Type	85 °C	-40 °C	0.0005000000237487257 A	3.4999999860146898e-12 F	2 ul	0.03200000151991844 A, 0.06400000303983688 A	Standard	5.099999977886682e-9 s	5.5 V	4.5 V	Positive Edge

Key Features

• Members of the Texas Instruments WidebusTMFamilyState-of-the-Art EPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Thin Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.Members of the Texas Instruments WidebusTMFamilyState-of-the-Art EPIC-IIBTMBiCMOS Design Significantly Reduces Power DissipationESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Typical VOLP(Output Ground Bounce) < 1 V at VCC= 5 V, TA= 25°CDistributed VCCand GND Pin Configuration Minimizes High-Speed Switching NoiseFlow-Through Architecture Optimizes PCB LayoutHigh-Drive Outputs (-32-mA IOH, 64-mA IOL)Package Options Include Plastic Thin Shrink Small-Outline (DGG), 300-mil Shrink Small-Outline (DL) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center SpacingsWidebus and EPIC-IIB are trademarks of Texas Instruments Incorporated.

Description

These 20-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The 'ABT16821 can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable () input can be used to place the ten outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16821 is characterized for operation from -40°C to 85°C. These 20-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The 'ABT16821 can be used as two 10-bit flip-flops or one 20-bit flip-flop. The 20 flip-flops are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable () input can be used to place the ten outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16821 is characterized for operation from -40°C to 85°C.