CD74HC73 Series
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
| Part | Input Capacitance | Mounting Type | Output Type | Current - Output High, Low | Clock Frequency | Type | Operating Temperature [Min] | Operating Temperature [Max] | Max Propagation Delay @ V, Max CL | Number of Bits per Element | Current - Quiescent (Iq) | Function | Number of Elements [custom] | Package / Case | Package / Case | Package / Case | Trigger Type | Voltage - Supply [Min] | Voltage - Supply [Max] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HC73M96 | 10 pF | Surface Mount | Complementary | 5.2 mA, 5.2 mA | 60 MHz | JK Type | -55 C | 125 °C | 28 ns | 1 | 4 çA | Reset | 2 | 3.9 mm | 0.154 in | 14-SOIC | Negative Edge | 2 V | 6 V |
Texas Instruments CD74HC73M | 10 pF | Surface Mount | Complementary | 5.2 mA, 5.2 mA | 60 MHz | JK Type | -55 C | 125 °C | 28 ns | 1 | 4 çA | Reset | 2 | 3.9 mm | 0.154 in | 14-SOIC | Negative Edge | 2 V | 6 V |
Texas Instruments CD74HC73MT | 10 pF | Surface Mount | Complementary | 5.2 mA, 5.2 mA | 60 MHz | JK Type | -55 C | 125 °C | 28 ns | 1 | 4 çA | Reset | 2 | 3.9 mm | 0.154 in | 14-SOIC | Negative Edge | 2 V | 6 V |
Texas Instruments CD74HC73E | 10 pF | Through Hole | Complementary | 5.2 mA, 5.2 mA | 60 MHz | JK Type | -55 C | 125 °C | 28 ns | 1 | 4 çA | Reset | 2 | 7.62 mm | 0.3 in | 14-DIP | Negative Edge | 2 V | 6 V |
Key Features
• Hysteresis on clock inputs for improved noise immunity and increased input rise and fall timesAsynchronous resetComplementary outputsBuffered inputsTypical fMAX= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOHHysteresis on clock inputs for improved noise immunity and increased input rise and fall timesAsynchronous resetComplementary outputsBuffered inputsTypical fMAX= 60 MHz at VCC= 5 V, CL= 15 pF, TA= 25℃Fanout (over temperature range)Standard outputs: 10 LSTTL loadsBus driver outputs: 15 LSTTL loadsWide operating temperature range: –55℃ to 125℃Balanced propagation delay and transition timesSignificant power reduction compared to LSTTL Logic ICsHC types2 V to 6V operationHigh noise immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5 VHCT types4.5 V to 5.5 V operationDirect LSTTL input logic compatibility, VIL= 0.8 V (max), VIH= 2 V (min)CMOS input compatibility, II≤ 1 µA at VOL, VOH